clang  10.0.0git
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
26 #define BUILTIN(ID, TYPE, ATTRS) \
27  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
29  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
31  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS) \
35  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
37  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
39  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
45  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
46  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
47  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
48  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
49  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
50  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
51  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
52  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
53  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
54  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
55  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
56  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
57  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
58  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
59  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
60  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
61  "k2", "k3", "k4", "k5", "k6", "k7",
62  "cr0", "cr2", "cr3", "cr4", "cr8",
63  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
64  "bnd0", "bnd1", "bnd2", "bnd3",
65 };
66 
68  {{"al", "ah", "eax", "rax"}, 0},
69  {{"bl", "bh", "ebx", "rbx"}, 3},
70  {{"cl", "ch", "ecx", "rcx"}, 2},
71  {{"dl", "dh", "edx", "rdx"}, 1},
72  {{"esi", "rsi"}, 4},
73  {{"edi", "rdi"}, 5},
74  {{"esp", "rsp"}, 7},
75  {{"ebp", "rbp"}, 6},
76  {{"r8d", "r8w", "r8b"}, 38},
77  {{"r9d", "r9w", "r9b"}, 39},
78  {{"r10d", "r10w", "r10b"}, 40},
79  {{"r11d", "r11w", "r11b"}, 41},
80  {{"r12d", "r12w", "r12b"}, 42},
81  {{"r13d", "r13w", "r13b"}, 43},
82  {{"r14d", "r14w", "r14b"}, 44},
83  {{"r15d", "r15w", "r15b"}, 45},
84 };
85 
86 } // namespace targets
87 } // namespace clang
88 
89 using namespace clang;
90 using namespace clang::targets;
91 
92 bool X86TargetInfo::setFPMath(StringRef Name) {
93  if (Name == "387") {
94  FPMath = FP_387;
95  return true;
96  }
97  if (Name == "sse") {
98  FPMath = FP_SSE;
99  return true;
100  }
101  return false;
102 }
103 
105  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
106  const std::vector<std::string> &FeaturesVec) const {
107  // FIXME: This *really* should not be here.
108  // X86_64 always has SSE2.
109  if (getTriple().getArch() == llvm::Triple::x86_64)
110  setFeatureEnabledImpl(Features, "sse2", true);
111 
112  const CPUKind Kind = getCPUKind(CPU);
113 
114  // Enable X87 for all X86 processors but Lakemont.
115  if (Kind != CK_Lakemont)
116  setFeatureEnabledImpl(Features, "x87", true);
117 
118  // Enable cmpxchg8 for i586 and greater CPUs. Include generic for backwards
119  // compatibility.
120  if (Kind >= CK_i586 || Kind == CK_Generic)
121  setFeatureEnabledImpl(Features, "cx8", true);
122 
123  switch (Kind) {
124  case CK_Generic:
125  case CK_i386:
126  case CK_i486:
127  case CK_i586:
128  case CK_Pentium:
129  case CK_PentiumPro:
130  case CK_i686:
131  case CK_Lakemont:
132  break;
133 
134  case CK_Cooperlake:
135  // CPX inherits all CLX features plus AVX512BF16
136  setFeatureEnabledImpl(Features, "avx512bf16", true);
137  LLVM_FALLTHROUGH;
138  case CK_Cascadelake:
139  // CLX inherits all SKX features plus AVX512VNNI
140  setFeatureEnabledImpl(Features, "avx512vnni", true);
141  LLVM_FALLTHROUGH;
142  case CK_SkylakeServer:
143  setFeatureEnabledImpl(Features, "avx512f", true);
144  setFeatureEnabledImpl(Features, "avx512cd", true);
145  setFeatureEnabledImpl(Features, "avx512dq", true);
146  setFeatureEnabledImpl(Features, "avx512bw", true);
147  setFeatureEnabledImpl(Features, "avx512vl", true);
148  setFeatureEnabledImpl(Features, "clwb", true);
149  setFeatureEnabledImpl(Features, "pku", true);
150  // SkylakeServer cores inherits all SKL features, except SGX
151  goto SkylakeCommon;
152 
153  case CK_Tigerlake:
154  setFeatureEnabledImpl(Features, "avx512vp2intersect", true);
155  setFeatureEnabledImpl(Features, "movdiri", true);
156  setFeatureEnabledImpl(Features, "movdir64b", true);
157  setFeatureEnabledImpl(Features, "shstk", true);
158  // Tigerlake cores inherits IcelakeClient, except pconfig and wbnoinvd
159  goto IcelakeCommon;
160 
161  case CK_IcelakeServer:
162  setFeatureEnabledImpl(Features, "pconfig", true);
163  setFeatureEnabledImpl(Features, "wbnoinvd", true);
164  LLVM_FALLTHROUGH;
165  case CK_IcelakeClient:
166 IcelakeCommon:
167  setFeatureEnabledImpl(Features, "vaes", true);
168  setFeatureEnabledImpl(Features, "gfni", true);
169  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
170  setFeatureEnabledImpl(Features, "avx512bitalg", true);
171  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
172  setFeatureEnabledImpl(Features, "avx512vnni", true);
173  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
174  setFeatureEnabledImpl(Features, "rdpid", true);
175  setFeatureEnabledImpl(Features, "clwb", true);
176  LLVM_FALLTHROUGH;
177  case CK_Cannonlake:
178  setFeatureEnabledImpl(Features, "avx512f", true);
179  setFeatureEnabledImpl(Features, "avx512cd", true);
180  setFeatureEnabledImpl(Features, "avx512dq", true);
181  setFeatureEnabledImpl(Features, "avx512bw", true);
182  setFeatureEnabledImpl(Features, "avx512vl", true);
183  setFeatureEnabledImpl(Features, "avx512ifma", true);
184  setFeatureEnabledImpl(Features, "avx512vbmi", true);
185  setFeatureEnabledImpl(Features, "pku", true);
186  setFeatureEnabledImpl(Features, "sha", true);
187  LLVM_FALLTHROUGH;
188  case CK_SkylakeClient:
189  setFeatureEnabledImpl(Features, "sgx", true);
190  // SkylakeServer cores inherits all SKL features, except SGX
191 SkylakeCommon:
192  setFeatureEnabledImpl(Features, "xsavec", true);
193  setFeatureEnabledImpl(Features, "xsaves", true);
194  setFeatureEnabledImpl(Features, "clflushopt", true);
195  setFeatureEnabledImpl(Features, "aes", true);
196  LLVM_FALLTHROUGH;
197  case CK_Broadwell:
198  setFeatureEnabledImpl(Features, "rdseed", true);
199  setFeatureEnabledImpl(Features, "adx", true);
200  setFeatureEnabledImpl(Features, "prfchw", true);
201  LLVM_FALLTHROUGH;
202  case CK_Haswell:
203  setFeatureEnabledImpl(Features, "avx2", true);
204  setFeatureEnabledImpl(Features, "lzcnt", true);
205  setFeatureEnabledImpl(Features, "bmi", true);
206  setFeatureEnabledImpl(Features, "bmi2", true);
207  setFeatureEnabledImpl(Features, "fma", true);
208  setFeatureEnabledImpl(Features, "invpcid", true);
209  setFeatureEnabledImpl(Features, "movbe", true);
210  LLVM_FALLTHROUGH;
211  case CK_IvyBridge:
212  setFeatureEnabledImpl(Features, "rdrnd", true);
213  setFeatureEnabledImpl(Features, "f16c", true);
214  setFeatureEnabledImpl(Features, "fsgsbase", true);
215  LLVM_FALLTHROUGH;
216  case CK_SandyBridge:
217  setFeatureEnabledImpl(Features, "avx", true);
218  setFeatureEnabledImpl(Features, "xsave", true);
219  setFeatureEnabledImpl(Features, "xsaveopt", true);
220  LLVM_FALLTHROUGH;
221  case CK_Westmere:
222  setFeatureEnabledImpl(Features, "pclmul", true);
223  LLVM_FALLTHROUGH;
224  case CK_Nehalem:
225  setFeatureEnabledImpl(Features, "sse4.2", true);
226  LLVM_FALLTHROUGH;
227  case CK_Penryn:
228  setFeatureEnabledImpl(Features, "sse4.1", true);
229  LLVM_FALLTHROUGH;
230  case CK_Core2:
231  setFeatureEnabledImpl(Features, "ssse3", true);
232  setFeatureEnabledImpl(Features, "sahf", true);
233  LLVM_FALLTHROUGH;
234  case CK_Nocona:
235  setFeatureEnabledImpl(Features, "cx16", true);
236  LLVM_FALLTHROUGH;
237  case CK_Yonah:
238  case CK_Prescott:
239  setFeatureEnabledImpl(Features, "sse3", true);
240  LLVM_FALLTHROUGH;
241  case CK_PentiumM:
242  case CK_Pentium4:
243  case CK_x86_64:
244  setFeatureEnabledImpl(Features, "sse2", true);
245  LLVM_FALLTHROUGH;
246  case CK_Pentium3:
247  case CK_C3_2:
248  setFeatureEnabledImpl(Features, "sse", true);
249  LLVM_FALLTHROUGH;
250  case CK_Pentium2:
251  setFeatureEnabledImpl(Features, "fxsr", true);
252  LLVM_FALLTHROUGH;
253  case CK_PentiumMMX:
254  case CK_K6:
255  case CK_WinChipC6:
256  setFeatureEnabledImpl(Features, "mmx", true);
257  break;
258 
259  case CK_Tremont:
260  setFeatureEnabledImpl(Features, "cldemote", true);
261  setFeatureEnabledImpl(Features, "movdiri", true);
262  setFeatureEnabledImpl(Features, "movdir64b", true);
263  setFeatureEnabledImpl(Features, "gfni", true);
264  setFeatureEnabledImpl(Features, "waitpkg", true);
265  LLVM_FALLTHROUGH;
266  case CK_GoldmontPlus:
267  setFeatureEnabledImpl(Features, "ptwrite", true);
268  setFeatureEnabledImpl(Features, "rdpid", true);
269  setFeatureEnabledImpl(Features, "sgx", true);
270  LLVM_FALLTHROUGH;
271  case CK_Goldmont:
272  setFeatureEnabledImpl(Features, "sha", true);
273  setFeatureEnabledImpl(Features, "rdseed", true);
274  setFeatureEnabledImpl(Features, "xsave", true);
275  setFeatureEnabledImpl(Features, "xsaveopt", true);
276  setFeatureEnabledImpl(Features, "xsavec", true);
277  setFeatureEnabledImpl(Features, "xsaves", true);
278  setFeatureEnabledImpl(Features, "clflushopt", true);
279  setFeatureEnabledImpl(Features, "fsgsbase", true);
280  setFeatureEnabledImpl(Features, "aes", true);
281  LLVM_FALLTHROUGH;
282  case CK_Silvermont:
283  setFeatureEnabledImpl(Features, "rdrnd", true);
284  setFeatureEnabledImpl(Features, "pclmul", true);
285  setFeatureEnabledImpl(Features, "sse4.2", true);
286  setFeatureEnabledImpl(Features, "prfchw", true);
287  LLVM_FALLTHROUGH;
288  case CK_Bonnell:
289  setFeatureEnabledImpl(Features, "movbe", true);
290  setFeatureEnabledImpl(Features, "ssse3", true);
291  setFeatureEnabledImpl(Features, "fxsr", true);
292  setFeatureEnabledImpl(Features, "cx16", true);
293  setFeatureEnabledImpl(Features, "sahf", true);
294  setFeatureEnabledImpl(Features, "mmx", true);
295  break;
296 
297  case CK_KNM:
298  // TODO: Add avx5124fmaps/avx5124vnniw.
299  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
300  LLVM_FALLTHROUGH;
301  case CK_KNL:
302  setFeatureEnabledImpl(Features, "avx512f", true);
303  setFeatureEnabledImpl(Features, "avx512cd", true);
304  setFeatureEnabledImpl(Features, "avx512er", true);
305  setFeatureEnabledImpl(Features, "avx512pf", true);
306  setFeatureEnabledImpl(Features, "prfchw", true);
307  setFeatureEnabledImpl(Features, "prefetchwt1", true);
308  setFeatureEnabledImpl(Features, "fxsr", true);
309  setFeatureEnabledImpl(Features, "rdseed", true);
310  setFeatureEnabledImpl(Features, "adx", true);
311  setFeatureEnabledImpl(Features, "lzcnt", true);
312  setFeatureEnabledImpl(Features, "bmi", true);
313  setFeatureEnabledImpl(Features, "bmi2", true);
314  setFeatureEnabledImpl(Features, "fma", true);
315  setFeatureEnabledImpl(Features, "rdrnd", true);
316  setFeatureEnabledImpl(Features, "f16c", true);
317  setFeatureEnabledImpl(Features, "fsgsbase", true);
318  setFeatureEnabledImpl(Features, "aes", true);
319  setFeatureEnabledImpl(Features, "pclmul", true);
320  setFeatureEnabledImpl(Features, "cx16", true);
321  setFeatureEnabledImpl(Features, "xsaveopt", true);
322  setFeatureEnabledImpl(Features, "xsave", true);
323  setFeatureEnabledImpl(Features, "movbe", true);
324  setFeatureEnabledImpl(Features, "sahf", true);
325  setFeatureEnabledImpl(Features, "mmx", true);
326  break;
327 
328  case CK_K6_2:
329  case CK_K6_3:
330  case CK_WinChip2:
331  case CK_C3:
332  setFeatureEnabledImpl(Features, "3dnow", true);
333  break;
334 
335  case CK_AMDFAM10:
336  setFeatureEnabledImpl(Features, "sse4a", true);
337  setFeatureEnabledImpl(Features, "lzcnt", true);
338  setFeatureEnabledImpl(Features, "popcnt", true);
339  setFeatureEnabledImpl(Features, "sahf", true);
340  LLVM_FALLTHROUGH;
341  case CK_K8SSE3:
342  setFeatureEnabledImpl(Features, "sse3", true);
343  LLVM_FALLTHROUGH;
344  case CK_K8:
345  setFeatureEnabledImpl(Features, "sse2", true);
346  LLVM_FALLTHROUGH;
347  case CK_AthlonXP:
348  setFeatureEnabledImpl(Features, "sse", true);
349  setFeatureEnabledImpl(Features, "fxsr", true);
350  LLVM_FALLTHROUGH;
351  case CK_Athlon:
352  case CK_Geode:
353  setFeatureEnabledImpl(Features, "3dnowa", true);
354  break;
355 
356  case CK_BTVER2:
357  setFeatureEnabledImpl(Features, "avx", true);
358  setFeatureEnabledImpl(Features, "aes", true);
359  setFeatureEnabledImpl(Features, "pclmul", true);
360  setFeatureEnabledImpl(Features, "bmi", true);
361  setFeatureEnabledImpl(Features, "f16c", true);
362  setFeatureEnabledImpl(Features, "xsaveopt", true);
363  setFeatureEnabledImpl(Features, "movbe", true);
364  LLVM_FALLTHROUGH;
365  case CK_BTVER1:
366  setFeatureEnabledImpl(Features, "ssse3", true);
367  setFeatureEnabledImpl(Features, "sse4a", true);
368  setFeatureEnabledImpl(Features, "lzcnt", true);
369  setFeatureEnabledImpl(Features, "popcnt", true);
370  setFeatureEnabledImpl(Features, "prfchw", true);
371  setFeatureEnabledImpl(Features, "cx16", true);
372  setFeatureEnabledImpl(Features, "fxsr", true);
373  setFeatureEnabledImpl(Features, "sahf", true);
374  setFeatureEnabledImpl(Features, "mmx", true);
375  break;
376 
377  case CK_ZNVER2:
378  setFeatureEnabledImpl(Features, "clwb", true);
379  setFeatureEnabledImpl(Features, "rdpid", true);
380  setFeatureEnabledImpl(Features, "wbnoinvd", true);
381  LLVM_FALLTHROUGH;
382  case CK_ZNVER1:
383  setFeatureEnabledImpl(Features, "adx", true);
384  setFeatureEnabledImpl(Features, "aes", true);
385  setFeatureEnabledImpl(Features, "avx2", true);
386  setFeatureEnabledImpl(Features, "bmi", true);
387  setFeatureEnabledImpl(Features, "bmi2", true);
388  setFeatureEnabledImpl(Features, "clflushopt", true);
389  setFeatureEnabledImpl(Features, "clzero", true);
390  setFeatureEnabledImpl(Features, "cx16", true);
391  setFeatureEnabledImpl(Features, "f16c", true);
392  setFeatureEnabledImpl(Features, "fma", true);
393  setFeatureEnabledImpl(Features, "fsgsbase", true);
394  setFeatureEnabledImpl(Features, "fxsr", true);
395  setFeatureEnabledImpl(Features, "lzcnt", true);
396  setFeatureEnabledImpl(Features, "mmx", true);
397  setFeatureEnabledImpl(Features, "mwaitx", true);
398  setFeatureEnabledImpl(Features, "movbe", true);
399  setFeatureEnabledImpl(Features, "pclmul", true);
400  setFeatureEnabledImpl(Features, "popcnt", true);
401  setFeatureEnabledImpl(Features, "prfchw", true);
402  setFeatureEnabledImpl(Features, "rdrnd", true);
403  setFeatureEnabledImpl(Features, "rdseed", true);
404  setFeatureEnabledImpl(Features, "sahf", true);
405  setFeatureEnabledImpl(Features, "sha", true);
406  setFeatureEnabledImpl(Features, "sse4a", true);
407  setFeatureEnabledImpl(Features, "xsave", true);
408  setFeatureEnabledImpl(Features, "xsavec", true);
409  setFeatureEnabledImpl(Features, "xsaveopt", true);
410  setFeatureEnabledImpl(Features, "xsaves", true);
411  break;
412 
413  case CK_BDVER4:
414  setFeatureEnabledImpl(Features, "avx2", true);
415  setFeatureEnabledImpl(Features, "bmi2", true);
416  setFeatureEnabledImpl(Features, "mwaitx", true);
417  LLVM_FALLTHROUGH;
418  case CK_BDVER3:
419  setFeatureEnabledImpl(Features, "fsgsbase", true);
420  setFeatureEnabledImpl(Features, "xsaveopt", true);
421  LLVM_FALLTHROUGH;
422  case CK_BDVER2:
423  setFeatureEnabledImpl(Features, "bmi", true);
424  setFeatureEnabledImpl(Features, "fma", true);
425  setFeatureEnabledImpl(Features, "f16c", true);
426  setFeatureEnabledImpl(Features, "tbm", true);
427  LLVM_FALLTHROUGH;
428  case CK_BDVER1:
429  // xop implies avx, sse4a and fma4.
430  setFeatureEnabledImpl(Features, "xop", true);
431  setFeatureEnabledImpl(Features, "lwp", true);
432  setFeatureEnabledImpl(Features, "lzcnt", true);
433  setFeatureEnabledImpl(Features, "aes", true);
434  setFeatureEnabledImpl(Features, "pclmul", true);
435  setFeatureEnabledImpl(Features, "prfchw", true);
436  setFeatureEnabledImpl(Features, "cx16", true);
437  setFeatureEnabledImpl(Features, "fxsr", true);
438  setFeatureEnabledImpl(Features, "xsave", true);
439  setFeatureEnabledImpl(Features, "sahf", true);
440  setFeatureEnabledImpl(Features, "mmx", true);
441  break;
442  }
443  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
444  return false;
445 
446  // Can't do this earlier because we need to be able to explicitly enable
447  // or disable these features and the things that they depend upon.
448 
449  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
450  auto I = Features.find("sse4.2");
451  if (I != Features.end() && I->getValue() &&
452  llvm::find(FeaturesVec, "-popcnt") == FeaturesVec.end())
453  Features["popcnt"] = true;
454 
455  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
456  I = Features.find("3dnow");
457  if (I != Features.end() && I->getValue() &&
458  llvm::find(FeaturesVec, "-prfchw") == FeaturesVec.end())
459  Features["prfchw"] = true;
460 
461  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
462  // then enable MMX.
463  I = Features.find("sse");
464  if (I != Features.end() && I->getValue() &&
465  llvm::find(FeaturesVec, "-mmx") == FeaturesVec.end())
466  Features["mmx"] = true;
467 
468  return true;
469 }
470 
471 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
472  X86SSEEnum Level, bool Enabled) {
473  if (Enabled) {
474  switch (Level) {
475  case AVX512F:
476  Features["avx512f"] = true;
477  Features["fma"] = true;
478  Features["f16c"] = true;
479  LLVM_FALLTHROUGH;
480  case AVX2:
481  Features["avx2"] = true;
482  LLVM_FALLTHROUGH;
483  case AVX:
484  Features["avx"] = true;
485  Features["xsave"] = true;
486  LLVM_FALLTHROUGH;
487  case SSE42:
488  Features["sse4.2"] = true;
489  LLVM_FALLTHROUGH;
490  case SSE41:
491  Features["sse4.1"] = true;
492  LLVM_FALLTHROUGH;
493  case SSSE3:
494  Features["ssse3"] = true;
495  LLVM_FALLTHROUGH;
496  case SSE3:
497  Features["sse3"] = true;
498  LLVM_FALLTHROUGH;
499  case SSE2:
500  Features["sse2"] = true;
501  LLVM_FALLTHROUGH;
502  case SSE1:
503  Features["sse"] = true;
504  LLVM_FALLTHROUGH;
505  case NoSSE:
506  break;
507  }
508  return;
509  }
510 
511  switch (Level) {
512  case NoSSE:
513  case SSE1:
514  Features["sse"] = false;
515  LLVM_FALLTHROUGH;
516  case SSE2:
517  Features["sse2"] = Features["pclmul"] = Features["aes"] = false;
518  Features["sha"] = Features["gfni"] = false;
519  LLVM_FALLTHROUGH;
520  case SSE3:
521  Features["sse3"] = false;
522  setXOPLevel(Features, NoXOP, false);
523  LLVM_FALLTHROUGH;
524  case SSSE3:
525  Features["ssse3"] = false;
526  LLVM_FALLTHROUGH;
527  case SSE41:
528  Features["sse4.1"] = false;
529  LLVM_FALLTHROUGH;
530  case SSE42:
531  Features["sse4.2"] = false;
532  LLVM_FALLTHROUGH;
533  case AVX:
534  Features["fma"] = Features["avx"] = Features["f16c"] = false;
535  Features["xsave"] = Features["xsaveopt"] = Features["vaes"] = false;
536  Features["vpclmulqdq"] = false;
537  setXOPLevel(Features, FMA4, false);
538  LLVM_FALLTHROUGH;
539  case AVX2:
540  Features["avx2"] = false;
541  LLVM_FALLTHROUGH;
542  case AVX512F:
543  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = false;
544  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = false;
545  Features["avx512vl"] = Features["avx512vbmi"] = false;
546  Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
547  Features["avx512bitalg"] = Features["avx512vnni"] = false;
548  Features["avx512vbmi2"] = Features["avx512bf16"] = false;
549  Features["avx512vp2intersect"] = false;
550  break;
551  }
552 }
553 
554 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
555  MMX3DNowEnum Level, bool Enabled) {
556  if (Enabled) {
557  switch (Level) {
558  case AMD3DNowAthlon:
559  Features["3dnowa"] = true;
560  LLVM_FALLTHROUGH;
561  case AMD3DNow:
562  Features["3dnow"] = true;
563  LLVM_FALLTHROUGH;
564  case MMX:
565  Features["mmx"] = true;
566  LLVM_FALLTHROUGH;
567  case NoMMX3DNow:
568  break;
569  }
570  return;
571  }
572 
573  switch (Level) {
574  case NoMMX3DNow:
575  case MMX:
576  Features["mmx"] = false;
577  LLVM_FALLTHROUGH;
578  case AMD3DNow:
579  Features["3dnow"] = false;
580  LLVM_FALLTHROUGH;
581  case AMD3DNowAthlon:
582  Features["3dnowa"] = false;
583  break;
584  }
585 }
586 
587 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
588  bool Enabled) {
589  if (Enabled) {
590  switch (Level) {
591  case XOP:
592  Features["xop"] = true;
593  LLVM_FALLTHROUGH;
594  case FMA4:
595  Features["fma4"] = true;
596  setSSELevel(Features, AVX, true);
597  LLVM_FALLTHROUGH;
598  case SSE4A:
599  Features["sse4a"] = true;
600  setSSELevel(Features, SSE3, true);
601  LLVM_FALLTHROUGH;
602  case NoXOP:
603  break;
604  }
605  return;
606  }
607 
608  switch (Level) {
609  case NoXOP:
610  case SSE4A:
611  Features["sse4a"] = false;
612  LLVM_FALLTHROUGH;
613  case FMA4:
614  Features["fma4"] = false;
615  LLVM_FALLTHROUGH;
616  case XOP:
617  Features["xop"] = false;
618  break;
619  }
620 }
621 
622 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
623  StringRef Name, bool Enabled) {
624  // This is a bit of a hack to deal with the sse4 target feature when used
625  // as part of the target attribute. We handle sse4 correctly everywhere
626  // else. See below for more information on how we handle the sse4 options.
627  if (Name != "sse4")
628  Features[Name] = Enabled;
629 
630  if (Name == "mmx") {
631  setMMXLevel(Features, MMX, Enabled);
632  } else if (Name == "sse") {
633  setSSELevel(Features, SSE1, Enabled);
634  } else if (Name == "sse2") {
635  setSSELevel(Features, SSE2, Enabled);
636  } else if (Name == "sse3") {
637  setSSELevel(Features, SSE3, Enabled);
638  } else if (Name == "ssse3") {
639  setSSELevel(Features, SSSE3, Enabled);
640  } else if (Name == "sse4.2") {
641  setSSELevel(Features, SSE42, Enabled);
642  } else if (Name == "sse4.1") {
643  setSSELevel(Features, SSE41, Enabled);
644  } else if (Name == "3dnow") {
645  setMMXLevel(Features, AMD3DNow, Enabled);
646  } else if (Name == "3dnowa") {
647  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
648  } else if (Name == "aes") {
649  if (Enabled)
650  setSSELevel(Features, SSE2, Enabled);
651  else
652  Features["vaes"] = false;
653  } else if (Name == "vaes") {
654  if (Enabled) {
655  setSSELevel(Features, AVX, Enabled);
656  Features["aes"] = true;
657  }
658  } else if (Name == "pclmul") {
659  if (Enabled)
660  setSSELevel(Features, SSE2, Enabled);
661  else
662  Features["vpclmulqdq"] = false;
663  } else if (Name == "vpclmulqdq") {
664  if (Enabled) {
665  setSSELevel(Features, AVX, Enabled);
666  Features["pclmul"] = true;
667  }
668  } else if (Name == "gfni") {
669  if (Enabled)
670  setSSELevel(Features, SSE2, Enabled);
671  } else if (Name == "avx") {
672  setSSELevel(Features, AVX, Enabled);
673  } else if (Name == "avx2") {
674  setSSELevel(Features, AVX2, Enabled);
675  } else if (Name == "avx512f") {
676  setSSELevel(Features, AVX512F, Enabled);
677  } else if (Name.startswith("avx512")) {
678  if (Enabled)
679  setSSELevel(Features, AVX512F, Enabled);
680  // Enable BWI instruction if certain features are being enabled.
681  if ((Name == "avx512vbmi" || Name == "avx512vbmi2" ||
682  Name == "avx512bitalg" || Name == "avx512bf16") && Enabled)
683  Features["avx512bw"] = true;
684  // Also disable some features if BWI is being disabled.
685  if (Name == "avx512bw" && !Enabled) {
686  Features["avx512vbmi"] = false;
687  Features["avx512vbmi2"] = false;
688  Features["avx512bitalg"] = false;
689  Features["avx512bf16"] = false;
690  }
691  } else if (Name == "fma") {
692  if (Enabled)
693  setSSELevel(Features, AVX, Enabled);
694  else
695  setSSELevel(Features, AVX512F, Enabled);
696  } else if (Name == "fma4") {
697  setXOPLevel(Features, FMA4, Enabled);
698  } else if (Name == "xop") {
699  setXOPLevel(Features, XOP, Enabled);
700  } else if (Name == "sse4a") {
701  setXOPLevel(Features, SSE4A, Enabled);
702  } else if (Name == "f16c") {
703  if (Enabled)
704  setSSELevel(Features, AVX, Enabled);
705  else
706  setSSELevel(Features, AVX512F, Enabled);
707  } else if (Name == "sha") {
708  if (Enabled)
709  setSSELevel(Features, SSE2, Enabled);
710  } else if (Name == "sse4") {
711  // We can get here via the __target__ attribute since that's not controlled
712  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
713  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
714  // disabled.
715  if (Enabled)
716  setSSELevel(Features, SSE42, Enabled);
717  else
718  setSSELevel(Features, SSE41, Enabled);
719  } else if (Name == "xsave") {
720  if (!Enabled)
721  Features["xsaveopt"] = false;
722  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
723  if (Enabled)
724  Features["xsave"] = true;
725  }
726 }
727 
728 /// handleTargetFeatures - Perform initialization based on the user
729 /// configured set of features.
730 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
731  DiagnosticsEngine &Diags) {
732  for (const auto &Feature : Features) {
733  if (Feature[0] != '+')
734  continue;
735 
736  if (Feature == "+aes") {
737  HasAES = true;
738  } else if (Feature == "+vaes") {
739  HasVAES = true;
740  } else if (Feature == "+pclmul") {
741  HasPCLMUL = true;
742  } else if (Feature == "+vpclmulqdq") {
743  HasVPCLMULQDQ = true;
744  } else if (Feature == "+lzcnt") {
745  HasLZCNT = true;
746  } else if (Feature == "+rdrnd") {
747  HasRDRND = true;
748  } else if (Feature == "+fsgsbase") {
749  HasFSGSBASE = true;
750  } else if (Feature == "+bmi") {
751  HasBMI = true;
752  } else if (Feature == "+bmi2") {
753  HasBMI2 = true;
754  } else if (Feature == "+popcnt") {
755  HasPOPCNT = true;
756  } else if (Feature == "+rtm") {
757  HasRTM = true;
758  } else if (Feature == "+prfchw") {
759  HasPRFCHW = true;
760  } else if (Feature == "+rdseed") {
761  HasRDSEED = true;
762  } else if (Feature == "+adx") {
763  HasADX = true;
764  } else if (Feature == "+tbm") {
765  HasTBM = true;
766  } else if (Feature == "+lwp") {
767  HasLWP = true;
768  } else if (Feature == "+fma") {
769  HasFMA = true;
770  } else if (Feature == "+f16c") {
771  HasF16C = true;
772  } else if (Feature == "+gfni") {
773  HasGFNI = true;
774  } else if (Feature == "+avx512cd") {
775  HasAVX512CD = true;
776  } else if (Feature == "+avx512vpopcntdq") {
777  HasAVX512VPOPCNTDQ = true;
778  } else if (Feature == "+avx512vnni") {
779  HasAVX512VNNI = true;
780  } else if (Feature == "+avx512bf16") {
781  HasAVX512BF16 = true;
782  } else if (Feature == "+avx512er") {
783  HasAVX512ER = true;
784  } else if (Feature == "+avx512pf") {
785  HasAVX512PF = true;
786  } else if (Feature == "+avx512dq") {
787  HasAVX512DQ = true;
788  } else if (Feature == "+avx512bitalg") {
789  HasAVX512BITALG = true;
790  } else if (Feature == "+avx512bw") {
791  HasAVX512BW = true;
792  } else if (Feature == "+avx512vl") {
793  HasAVX512VL = true;
794  } else if (Feature == "+avx512vbmi") {
795  HasAVX512VBMI = true;
796  } else if (Feature == "+avx512vbmi2") {
797  HasAVX512VBMI2 = true;
798  } else if (Feature == "+avx512ifma") {
799  HasAVX512IFMA = true;
800  } else if (Feature == "+avx512vp2intersect") {
801  HasAVX512VP2INTERSECT = true;
802  } else if (Feature == "+sha") {
803  HasSHA = true;
804  } else if (Feature == "+shstk") {
805  HasSHSTK = true;
806  } else if (Feature == "+movbe") {
807  HasMOVBE = true;
808  } else if (Feature == "+sgx") {
809  HasSGX = true;
810  } else if (Feature == "+cx8") {
811  HasCX8 = true;
812  } else if (Feature == "+cx16") {
813  HasCX16 = true;
814  } else if (Feature == "+fxsr") {
815  HasFXSR = true;
816  } else if (Feature == "+xsave") {
817  HasXSAVE = true;
818  } else if (Feature == "+xsaveopt") {
819  HasXSAVEOPT = true;
820  } else if (Feature == "+xsavec") {
821  HasXSAVEC = true;
822  } else if (Feature == "+xsaves") {
823  HasXSAVES = true;
824  } else if (Feature == "+mwaitx") {
825  HasMWAITX = true;
826  } else if (Feature == "+pku") {
827  HasPKU = true;
828  } else if (Feature == "+clflushopt") {
829  HasCLFLUSHOPT = true;
830  } else if (Feature == "+clwb") {
831  HasCLWB = true;
832  } else if (Feature == "+wbnoinvd") {
833  HasWBNOINVD = true;
834  } else if (Feature == "+prefetchwt1") {
835  HasPREFETCHWT1 = true;
836  } else if (Feature == "+clzero") {
837  HasCLZERO = true;
838  } else if (Feature == "+cldemote") {
839  HasCLDEMOTE = true;
840  } else if (Feature == "+rdpid") {
841  HasRDPID = true;
842  } else if (Feature == "+retpoline-external-thunk") {
843  HasRetpolineExternalThunk = true;
844  } else if (Feature == "+sahf") {
845  HasLAHFSAHF = true;
846  } else if (Feature == "+waitpkg") {
847  HasWAITPKG = true;
848  } else if (Feature == "+movdiri") {
849  HasMOVDIRI = true;
850  } else if (Feature == "+movdir64b") {
851  HasMOVDIR64B = true;
852  } else if (Feature == "+pconfig") {
853  HasPCONFIG = true;
854  } else if (Feature == "+ptwrite") {
855  HasPTWRITE = true;
856  } else if (Feature == "+invpcid") {
857  HasINVPCID = true;
858  } else if (Feature == "+enqcmd") {
859  HasENQCMD = true;
860  }
861 
862  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
863  .Case("+avx512f", AVX512F)
864  .Case("+avx2", AVX2)
865  .Case("+avx", AVX)
866  .Case("+sse4.2", SSE42)
867  .Case("+sse4.1", SSE41)
868  .Case("+ssse3", SSSE3)
869  .Case("+sse3", SSE3)
870  .Case("+sse2", SSE2)
871  .Case("+sse", SSE1)
872  .Default(NoSSE);
873  SSELevel = std::max(SSELevel, Level);
874 
875  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
876  .Case("+3dnowa", AMD3DNowAthlon)
877  .Case("+3dnow", AMD3DNow)
878  .Case("+mmx", MMX)
879  .Default(NoMMX3DNow);
880  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
881 
882  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
883  .Case("+xop", XOP)
884  .Case("+fma4", FMA4)
885  .Case("+sse4a", SSE4A)
886  .Default(NoXOP);
887  XOPLevel = std::max(XOPLevel, XLevel);
888  }
889 
890  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
891  // matches the selected sse level.
892  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
893  (FPMath == FP_387 && SSELevel >= SSE1)) {
894  Diags.Report(diag::err_target_unsupported_fpmath)
895  << (FPMath == FP_SSE ? "sse" : "387");
896  return false;
897  }
898 
899  SimdDefaultAlign =
900  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
901  return true;
902 }
903 
904 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
905 /// definitions for this particular subtarget.
907  MacroBuilder &Builder) const {
908  // Inline assembly supports X86 flag outputs.
909  Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
910 
911  std::string CodeModel = getTargetOpts().CodeModel;
912  if (CodeModel == "default")
913  CodeModel = "small";
914  Builder.defineMacro("__code_model_" + CodeModel + "_");
915 
916  // Target identification.
917  if (getTriple().getArch() == llvm::Triple::x86_64) {
918  Builder.defineMacro("__amd64__");
919  Builder.defineMacro("__amd64");
920  Builder.defineMacro("__x86_64");
921  Builder.defineMacro("__x86_64__");
922  if (getTriple().getArchName() == "x86_64h") {
923  Builder.defineMacro("__x86_64h");
924  Builder.defineMacro("__x86_64h__");
925  }
926  } else {
927  DefineStd(Builder, "i386", Opts);
928  }
929 
930  Builder.defineMacro("__SEG_GS");
931  Builder.defineMacro("__SEG_FS");
932  Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
933  Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
934 
935  // Subtarget options.
936  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
937  // truly should be based on -mtune options.
938  switch (CPU) {
939  case CK_Generic:
940  break;
941  case CK_i386:
942  // The rest are coming from the i386 define above.
943  Builder.defineMacro("__tune_i386__");
944  break;
945  case CK_i486:
946  case CK_WinChipC6:
947  case CK_WinChip2:
948  case CK_C3:
949  defineCPUMacros(Builder, "i486");
950  break;
951  case CK_PentiumMMX:
952  Builder.defineMacro("__pentium_mmx__");
953  Builder.defineMacro("__tune_pentium_mmx__");
954  LLVM_FALLTHROUGH;
955  case CK_i586:
956  case CK_Pentium:
957  defineCPUMacros(Builder, "i586");
958  defineCPUMacros(Builder, "pentium");
959  break;
960  case CK_Pentium3:
961  case CK_PentiumM:
962  Builder.defineMacro("__tune_pentium3__");
963  LLVM_FALLTHROUGH;
964  case CK_Pentium2:
965  case CK_C3_2:
966  Builder.defineMacro("__tune_pentium2__");
967  LLVM_FALLTHROUGH;
968  case CK_PentiumPro:
969  case CK_i686:
970  defineCPUMacros(Builder, "i686");
971  defineCPUMacros(Builder, "pentiumpro");
972  break;
973  case CK_Pentium4:
974  defineCPUMacros(Builder, "pentium4");
975  break;
976  case CK_Yonah:
977  case CK_Prescott:
978  case CK_Nocona:
979  defineCPUMacros(Builder, "nocona");
980  break;
981  case CK_Core2:
982  case CK_Penryn:
983  defineCPUMacros(Builder, "core2");
984  break;
985  case CK_Bonnell:
986  defineCPUMacros(Builder, "atom");
987  break;
988  case CK_Silvermont:
989  defineCPUMacros(Builder, "slm");
990  break;
991  case CK_Goldmont:
992  defineCPUMacros(Builder, "goldmont");
993  break;
994  case CK_GoldmontPlus:
995  defineCPUMacros(Builder, "goldmont_plus");
996  break;
997  case CK_Tremont:
998  defineCPUMacros(Builder, "tremont");
999  break;
1000  case CK_Nehalem:
1001  case CK_Westmere:
1002  case CK_SandyBridge:
1003  case CK_IvyBridge:
1004  case CK_Haswell:
1005  case CK_Broadwell:
1006  case CK_SkylakeClient:
1007  case CK_SkylakeServer:
1008  case CK_Cascadelake:
1009  case CK_Cooperlake:
1010  case CK_Cannonlake:
1011  case CK_IcelakeClient:
1012  case CK_IcelakeServer:
1013  case CK_Tigerlake:
1014  // FIXME: Historically, we defined this legacy name, it would be nice to
1015  // remove it at some point. We've never exposed fine-grained names for
1016  // recent primary x86 CPUs, and we should keep it that way.
1017  defineCPUMacros(Builder, "corei7");
1018  break;
1019  case CK_KNL:
1020  defineCPUMacros(Builder, "knl");
1021  break;
1022  case CK_KNM:
1023  break;
1024  case CK_Lakemont:
1025  defineCPUMacros(Builder, "i586", /*Tuning*/false);
1026  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
1027  Builder.defineMacro("__tune_lakemont__");
1028  break;
1029  case CK_K6_2:
1030  Builder.defineMacro("__k6_2__");
1031  Builder.defineMacro("__tune_k6_2__");
1032  LLVM_FALLTHROUGH;
1033  case CK_K6_3:
1034  if (CPU != CK_K6_2) { // In case of fallthrough
1035  // FIXME: GCC may be enabling these in cases where some other k6
1036  // architecture is specified but -m3dnow is explicitly provided. The
1037  // exact semantics need to be determined and emulated here.
1038  Builder.defineMacro("__k6_3__");
1039  Builder.defineMacro("__tune_k6_3__");
1040  }
1041  LLVM_FALLTHROUGH;
1042  case CK_K6:
1043  defineCPUMacros(Builder, "k6");
1044  break;
1045  case CK_Athlon:
1046  case CK_AthlonXP:
1047  defineCPUMacros(Builder, "athlon");
1048  if (SSELevel != NoSSE) {
1049  Builder.defineMacro("__athlon_sse__");
1050  Builder.defineMacro("__tune_athlon_sse__");
1051  }
1052  break;
1053  case CK_K8:
1054  case CK_K8SSE3:
1055  case CK_x86_64:
1056  defineCPUMacros(Builder, "k8");
1057  break;
1058  case CK_AMDFAM10:
1059  defineCPUMacros(Builder, "amdfam10");
1060  break;
1061  case CK_BTVER1:
1062  defineCPUMacros(Builder, "btver1");
1063  break;
1064  case CK_BTVER2:
1065  defineCPUMacros(Builder, "btver2");
1066  break;
1067  case CK_BDVER1:
1068  defineCPUMacros(Builder, "bdver1");
1069  break;
1070  case CK_BDVER2:
1071  defineCPUMacros(Builder, "bdver2");
1072  break;
1073  case CK_BDVER3:
1074  defineCPUMacros(Builder, "bdver3");
1075  break;
1076  case CK_BDVER4:
1077  defineCPUMacros(Builder, "bdver4");
1078  break;
1079  case CK_ZNVER1:
1080  defineCPUMacros(Builder, "znver1");
1081  break;
1082  case CK_ZNVER2:
1083  defineCPUMacros(Builder, "znver2");
1084  break;
1085  case CK_Geode:
1086  defineCPUMacros(Builder, "geode");
1087  break;
1088  }
1089 
1090  // Target properties.
1091  Builder.defineMacro("__REGISTER_PREFIX__", "");
1092 
1093  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
1094  // functions in glibc header files that use FP Stack inline asm which the
1095  // backend can't deal with (PR879).
1096  Builder.defineMacro("__NO_MATH_INLINES");
1097 
1098  if (HasAES)
1099  Builder.defineMacro("__AES__");
1100 
1101  if (HasVAES)
1102  Builder.defineMacro("__VAES__");
1103 
1104  if (HasPCLMUL)
1105  Builder.defineMacro("__PCLMUL__");
1106 
1107  if (HasVPCLMULQDQ)
1108  Builder.defineMacro("__VPCLMULQDQ__");
1109 
1110  if (HasLZCNT)
1111  Builder.defineMacro("__LZCNT__");
1112 
1113  if (HasRDRND)
1114  Builder.defineMacro("__RDRND__");
1115 
1116  if (HasFSGSBASE)
1117  Builder.defineMacro("__FSGSBASE__");
1118 
1119  if (HasBMI)
1120  Builder.defineMacro("__BMI__");
1121 
1122  if (HasBMI2)
1123  Builder.defineMacro("__BMI2__");
1124 
1125  if (HasPOPCNT)
1126  Builder.defineMacro("__POPCNT__");
1127 
1128  if (HasRTM)
1129  Builder.defineMacro("__RTM__");
1130 
1131  if (HasPRFCHW)
1132  Builder.defineMacro("__PRFCHW__");
1133 
1134  if (HasRDSEED)
1135  Builder.defineMacro("__RDSEED__");
1136 
1137  if (HasADX)
1138  Builder.defineMacro("__ADX__");
1139 
1140  if (HasTBM)
1141  Builder.defineMacro("__TBM__");
1142 
1143  if (HasLWP)
1144  Builder.defineMacro("__LWP__");
1145 
1146  if (HasMWAITX)
1147  Builder.defineMacro("__MWAITX__");
1148 
1149  if (HasMOVBE)
1150  Builder.defineMacro("__MOVBE__");
1151 
1152  switch (XOPLevel) {
1153  case XOP:
1154  Builder.defineMacro("__XOP__");
1155  LLVM_FALLTHROUGH;
1156  case FMA4:
1157  Builder.defineMacro("__FMA4__");
1158  LLVM_FALLTHROUGH;
1159  case SSE4A:
1160  Builder.defineMacro("__SSE4A__");
1161  LLVM_FALLTHROUGH;
1162  case NoXOP:
1163  break;
1164  }
1165 
1166  if (HasFMA)
1167  Builder.defineMacro("__FMA__");
1168 
1169  if (HasF16C)
1170  Builder.defineMacro("__F16C__");
1171 
1172  if (HasGFNI)
1173  Builder.defineMacro("__GFNI__");
1174 
1175  if (HasAVX512CD)
1176  Builder.defineMacro("__AVX512CD__");
1177  if (HasAVX512VPOPCNTDQ)
1178  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1179  if (HasAVX512VNNI)
1180  Builder.defineMacro("__AVX512VNNI__");
1181  if (HasAVX512BF16)
1182  Builder.defineMacro("__AVX512BF16__");
1183  if (HasAVX512ER)
1184  Builder.defineMacro("__AVX512ER__");
1185  if (HasAVX512PF)
1186  Builder.defineMacro("__AVX512PF__");
1187  if (HasAVX512DQ)
1188  Builder.defineMacro("__AVX512DQ__");
1189  if (HasAVX512BITALG)
1190  Builder.defineMacro("__AVX512BITALG__");
1191  if (HasAVX512BW)
1192  Builder.defineMacro("__AVX512BW__");
1193  if (HasAVX512VL)
1194  Builder.defineMacro("__AVX512VL__");
1195  if (HasAVX512VBMI)
1196  Builder.defineMacro("__AVX512VBMI__");
1197  if (HasAVX512VBMI2)
1198  Builder.defineMacro("__AVX512VBMI2__");
1199  if (HasAVX512IFMA)
1200  Builder.defineMacro("__AVX512IFMA__");
1201  if (HasAVX512VP2INTERSECT)
1202  Builder.defineMacro("__AVX512VP2INTERSECT__");
1203  if (HasSHA)
1204  Builder.defineMacro("__SHA__");
1205 
1206  if (HasFXSR)
1207  Builder.defineMacro("__FXSR__");
1208  if (HasXSAVE)
1209  Builder.defineMacro("__XSAVE__");
1210  if (HasXSAVEOPT)
1211  Builder.defineMacro("__XSAVEOPT__");
1212  if (HasXSAVEC)
1213  Builder.defineMacro("__XSAVEC__");
1214  if (HasXSAVES)
1215  Builder.defineMacro("__XSAVES__");
1216  if (HasPKU)
1217  Builder.defineMacro("__PKU__");
1218  if (HasCLFLUSHOPT)
1219  Builder.defineMacro("__CLFLUSHOPT__");
1220  if (HasCLWB)
1221  Builder.defineMacro("__CLWB__");
1222  if (HasWBNOINVD)
1223  Builder.defineMacro("__WBNOINVD__");
1224  if (HasSHSTK)
1225  Builder.defineMacro("__SHSTK__");
1226  if (HasSGX)
1227  Builder.defineMacro("__SGX__");
1228  if (HasPREFETCHWT1)
1229  Builder.defineMacro("__PREFETCHWT1__");
1230  if (HasCLZERO)
1231  Builder.defineMacro("__CLZERO__");
1232  if (HasRDPID)
1233  Builder.defineMacro("__RDPID__");
1234  if (HasCLDEMOTE)
1235  Builder.defineMacro("__CLDEMOTE__");
1236  if (HasWAITPKG)
1237  Builder.defineMacro("__WAITPKG__");
1238  if (HasMOVDIRI)
1239  Builder.defineMacro("__MOVDIRI__");
1240  if (HasMOVDIR64B)
1241  Builder.defineMacro("__MOVDIR64B__");
1242  if (HasPCONFIG)
1243  Builder.defineMacro("__PCONFIG__");
1244  if (HasPTWRITE)
1245  Builder.defineMacro("__PTWRITE__");
1246  if (HasINVPCID)
1247  Builder.defineMacro("__INVPCID__");
1248  if (HasENQCMD)
1249  Builder.defineMacro("__ENQCMD__");
1250 
1251  // Each case falls through to the previous one here.
1252  switch (SSELevel) {
1253  case AVX512F:
1254  Builder.defineMacro("__AVX512F__");
1255  LLVM_FALLTHROUGH;
1256  case AVX2:
1257  Builder.defineMacro("__AVX2__");
1258  LLVM_FALLTHROUGH;
1259  case AVX:
1260  Builder.defineMacro("__AVX__");
1261  LLVM_FALLTHROUGH;
1262  case SSE42:
1263  Builder.defineMacro("__SSE4_2__");
1264  LLVM_FALLTHROUGH;
1265  case SSE41:
1266  Builder.defineMacro("__SSE4_1__");
1267  LLVM_FALLTHROUGH;
1268  case SSSE3:
1269  Builder.defineMacro("__SSSE3__");
1270  LLVM_FALLTHROUGH;
1271  case SSE3:
1272  Builder.defineMacro("__SSE3__");
1273  LLVM_FALLTHROUGH;
1274  case SSE2:
1275  Builder.defineMacro("__SSE2__");
1276  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1277  LLVM_FALLTHROUGH;
1278  case SSE1:
1279  Builder.defineMacro("__SSE__");
1280  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1281  LLVM_FALLTHROUGH;
1282  case NoSSE:
1283  break;
1284  }
1285 
1286  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1287  switch (SSELevel) {
1288  case AVX512F:
1289  case AVX2:
1290  case AVX:
1291  case SSE42:
1292  case SSE41:
1293  case SSSE3:
1294  case SSE3:
1295  case SSE2:
1296  Builder.defineMacro("_M_IX86_FP", Twine(2));
1297  break;
1298  case SSE1:
1299  Builder.defineMacro("_M_IX86_FP", Twine(1));
1300  break;
1301  default:
1302  Builder.defineMacro("_M_IX86_FP", Twine(0));
1303  break;
1304  }
1305  }
1306 
1307  // Each case falls through to the previous one here.
1308  switch (MMX3DNowLevel) {
1309  case AMD3DNowAthlon:
1310  Builder.defineMacro("__3dNOW_A__");
1311  LLVM_FALLTHROUGH;
1312  case AMD3DNow:
1313  Builder.defineMacro("__3dNOW__");
1314  LLVM_FALLTHROUGH;
1315  case MMX:
1316  Builder.defineMacro("__MMX__");
1317  LLVM_FALLTHROUGH;
1318  case NoMMX3DNow:
1319  break;
1320  }
1321 
1322  if (CPU >= CK_i486 || CPU == CK_Generic) {
1323  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1324  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1325  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1326  }
1327  if (HasCX8)
1328  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1329  if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
1330  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1331 
1332  if (HasFloat128)
1333  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1334 }
1335 
1336 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1337  return llvm::StringSwitch<bool>(Name)
1338  .Case("3dnow", true)
1339  .Case("3dnowa", true)
1340  .Case("adx", true)
1341  .Case("aes", true)
1342  .Case("avx", true)
1343  .Case("avx2", true)
1344  .Case("avx512f", true)
1345  .Case("avx512cd", true)
1346  .Case("avx512vpopcntdq", true)
1347  .Case("avx512vnni", true)
1348  .Case("avx512bf16", true)
1349  .Case("avx512er", true)
1350  .Case("avx512pf", true)
1351  .Case("avx512dq", true)
1352  .Case("avx512bitalg", true)
1353  .Case("avx512bw", true)
1354  .Case("avx512vl", true)
1355  .Case("avx512vbmi", true)
1356  .Case("avx512vbmi2", true)
1357  .Case("avx512ifma", true)
1358  .Case("avx512vp2intersect", true)
1359  .Case("bmi", true)
1360  .Case("bmi2", true)
1361  .Case("cldemote", true)
1362  .Case("clflushopt", true)
1363  .Case("clwb", true)
1364  .Case("clzero", true)
1365  .Case("cx16", true)
1366  .Case("enqcmd", true)
1367  .Case("f16c", true)
1368  .Case("fma", true)
1369  .Case("fma4", true)
1370  .Case("fsgsbase", true)
1371  .Case("fxsr", true)
1372  .Case("gfni", true)
1373  .Case("invpcid", true)
1374  .Case("lwp", true)
1375  .Case("lzcnt", true)
1376  .Case("mmx", true)
1377  .Case("movbe", true)
1378  .Case("movdiri", true)
1379  .Case("movdir64b", true)
1380  .Case("mwaitx", true)
1381  .Case("pclmul", true)
1382  .Case("pconfig", true)
1383  .Case("pku", true)
1384  .Case("popcnt", true)
1385  .Case("prefetchwt1", true)
1386  .Case("prfchw", true)
1387  .Case("ptwrite", true)
1388  .Case("rdpid", true)
1389  .Case("rdrnd", true)
1390  .Case("rdseed", true)
1391  .Case("rtm", true)
1392  .Case("sahf", true)
1393  .Case("sgx", true)
1394  .Case("sha", true)
1395  .Case("shstk", true)
1396  .Case("sse", true)
1397  .Case("sse2", true)
1398  .Case("sse3", true)
1399  .Case("ssse3", true)
1400  .Case("sse4", true)
1401  .Case("sse4.1", true)
1402  .Case("sse4.2", true)
1403  .Case("sse4a", true)
1404  .Case("tbm", true)
1405  .Case("vaes", true)
1406  .Case("vpclmulqdq", true)
1407  .Case("wbnoinvd", true)
1408  .Case("waitpkg", true)
1409  .Case("x87", true)
1410  .Case("xop", true)
1411  .Case("xsave", true)
1412  .Case("xsavec", true)
1413  .Case("xsaves", true)
1414  .Case("xsaveopt", true)
1415  .Default(false);
1416 }
1417 
1418 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1419  return llvm::StringSwitch<bool>(Feature)
1420  .Case("adx", HasADX)
1421  .Case("aes", HasAES)
1422  .Case("avx", SSELevel >= AVX)
1423  .Case("avx2", SSELevel >= AVX2)
1424  .Case("avx512f", SSELevel >= AVX512F)
1425  .Case("avx512cd", HasAVX512CD)
1426  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1427  .Case("avx512vnni", HasAVX512VNNI)
1428  .Case("avx512bf16", HasAVX512BF16)
1429  .Case("avx512er", HasAVX512ER)
1430  .Case("avx512pf", HasAVX512PF)
1431  .Case("avx512dq", HasAVX512DQ)
1432  .Case("avx512bitalg", HasAVX512BITALG)
1433  .Case("avx512bw", HasAVX512BW)
1434  .Case("avx512vl", HasAVX512VL)
1435  .Case("avx512vbmi", HasAVX512VBMI)
1436  .Case("avx512vbmi2", HasAVX512VBMI2)
1437  .Case("avx512ifma", HasAVX512IFMA)
1438  .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
1439  .Case("bmi", HasBMI)
1440  .Case("bmi2", HasBMI2)
1441  .Case("cldemote", HasCLDEMOTE)
1442  .Case("clflushopt", HasCLFLUSHOPT)
1443  .Case("clwb", HasCLWB)
1444  .Case("clzero", HasCLZERO)
1445  .Case("cx8", HasCX8)
1446  .Case("cx16", HasCX16)
1447  .Case("enqcmd", HasENQCMD)
1448  .Case("f16c", HasF16C)
1449  .Case("fma", HasFMA)
1450  .Case("fma4", XOPLevel >= FMA4)
1451  .Case("fsgsbase", HasFSGSBASE)
1452  .Case("fxsr", HasFXSR)
1453  .Case("gfni", HasGFNI)
1454  .Case("invpcid", HasINVPCID)
1455  .Case("lwp", HasLWP)
1456  .Case("lzcnt", HasLZCNT)
1457  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1458  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1459  .Case("mmx", MMX3DNowLevel >= MMX)
1460  .Case("movbe", HasMOVBE)
1461  .Case("movdiri", HasMOVDIRI)
1462  .Case("movdir64b", HasMOVDIR64B)
1463  .Case("mwaitx", HasMWAITX)
1464  .Case("pclmul", HasPCLMUL)
1465  .Case("pconfig", HasPCONFIG)
1466  .Case("pku", HasPKU)
1467  .Case("popcnt", HasPOPCNT)
1468  .Case("prefetchwt1", HasPREFETCHWT1)
1469  .Case("prfchw", HasPRFCHW)
1470  .Case("ptwrite", HasPTWRITE)
1471  .Case("rdpid", HasRDPID)
1472  .Case("rdrnd", HasRDRND)
1473  .Case("rdseed", HasRDSEED)
1474  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1475  .Case("rtm", HasRTM)
1476  .Case("sahf", HasLAHFSAHF)
1477  .Case("sgx", HasSGX)
1478  .Case("sha", HasSHA)
1479  .Case("shstk", HasSHSTK)
1480  .Case("sse", SSELevel >= SSE1)
1481  .Case("sse2", SSELevel >= SSE2)
1482  .Case("sse3", SSELevel >= SSE3)
1483  .Case("ssse3", SSELevel >= SSSE3)
1484  .Case("sse4.1", SSELevel >= SSE41)
1485  .Case("sse4.2", SSELevel >= SSE42)
1486  .Case("sse4a", XOPLevel >= SSE4A)
1487  .Case("tbm", HasTBM)
1488  .Case("vaes", HasVAES)
1489  .Case("vpclmulqdq", HasVPCLMULQDQ)
1490  .Case("wbnoinvd", HasWBNOINVD)
1491  .Case("waitpkg", HasWAITPKG)
1492  .Case("x86", true)
1493  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1494  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1495  .Case("xop", XOPLevel >= XOP)
1496  .Case("xsave", HasXSAVE)
1497  .Case("xsavec", HasXSAVEC)
1498  .Case("xsaves", HasXSAVES)
1499  .Case("xsaveopt", HasXSAVEOPT)
1500  .Default(false);
1501 }
1502 
1503 // We can't use a generic validation scheme for the features accepted here
1504 // versus subtarget features accepted in the target attribute because the
1505 // bitfield structure that's initialized in the runtime only supports the
1506 // below currently rather than the full range of subtarget features. (See
1507 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1508 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1509  return llvm::StringSwitch<bool>(FeatureStr)
1510 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1511 #include "llvm/Support/X86TargetParser.def"
1512  .Default(false);
1513 }
1514 
1515 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1516  return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1517 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, llvm::X86::ENUM)
1518 #include "llvm/Support/X86TargetParser.def"
1519  ;
1520  // Note, this function should only be used after ensuring the value is
1521  // correct, so it asserts if the value is out of range.
1522 }
1523 
1524 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1525  enum class FeatPriority {
1526 #define FEATURE(FEAT) FEAT,
1527 #include "clang/Basic/X86Target.def"
1528  };
1529  switch (Feat) {
1530 #define FEATURE(FEAT) \
1531  case llvm::X86::FEAT: \
1532  return static_cast<unsigned>(FeatPriority::FEAT);
1533 #include "clang/Basic/X86Target.def"
1534  default:
1535  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1536  }
1537 }
1538 
1539 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1540  // Valid CPUs have a 'key feature' that compares just better than its key
1541  // feature.
1542  CPUKind Kind = getCPUKind(Name);
1543  if (Kind != CK_Generic) {
1544  switch (Kind) {
1545  default:
1546  llvm_unreachable(
1547  "CPU Type without a key feature used in 'target' attribute");
1548 #define PROC_WITH_FEAT(ENUM, STR, IS64, KEY_FEAT) \
1549  case CK_##ENUM: \
1550  return (getFeaturePriority(llvm::X86::KEY_FEAT) << 1) + 1;
1551 #include "clang/Basic/X86Target.def"
1552  }
1553  }
1554 
1555  // Now we know we have a feature, so get its priority and shift it a few so
1556  // that we have sufficient room for the CPUs (above).
1557  return getFeaturePriority(getFeature(Name)) << 1;
1558 }
1559 
1561  return llvm::StringSwitch<bool>(Name)
1562 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1563 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1564 #include "clang/Basic/X86Target.def"
1565  .Default(false);
1566 }
1567 
1568 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1569  return llvm::StringSwitch<StringRef>(Name)
1570 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1571 #include "clang/Basic/X86Target.def"
1572  .Default(Name);
1573 }
1574 
1576  return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1577 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1578 #include "clang/Basic/X86Target.def"
1579  .Default(0);
1580 }
1581 
1583  StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1584  StringRef WholeList =
1585  llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1586 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1587 #include "clang/Basic/X86Target.def"
1588  .Default("");
1589  WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1590 }
1591 
1592 // We can't use a generic validation scheme for the cpus accepted here
1593 // versus subtarget cpus accepted in the target attribute because the
1594 // variables intitialized by the runtime only support the below currently
1595 // rather than the full range of cpus.
1596 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1597  return llvm::StringSwitch<bool>(FeatureStr)
1598 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1599 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1600  .Cases(STR, ALIAS, true)
1601 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1602 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1603 #include "llvm/Support/X86TargetParser.def"
1604  .Default(false);
1605 }
1606 
1607 static unsigned matchAsmCCConstraint(const char *&Name) {
1608  auto RV = llvm::StringSwitch<unsigned>(Name)
1609  .Case("@cca", 4)
1610  .Case("@ccae", 5)
1611  .Case("@ccb", 4)
1612  .Case("@ccbe", 5)
1613  .Case("@ccc", 4)
1614  .Case("@cce", 4)
1615  .Case("@ccz", 4)
1616  .Case("@ccg", 4)
1617  .Case("@ccge", 5)
1618  .Case("@ccl", 4)
1619  .Case("@ccle", 5)
1620  .Case("@ccna", 5)
1621  .Case("@ccnae", 6)
1622  .Case("@ccnb", 5)
1623  .Case("@ccnbe", 6)
1624  .Case("@ccnc", 5)
1625  .Case("@ccne", 5)
1626  .Case("@ccnz", 5)
1627  .Case("@ccng", 5)
1628  .Case("@ccnge", 6)
1629  .Case("@ccnl", 5)
1630  .Case("@ccnle", 6)
1631  .Case("@ccno", 5)
1632  .Case("@ccnp", 5)
1633  .Case("@ccns", 5)
1634  .Case("@cco", 4)
1635  .Case("@ccp", 4)
1636  .Case("@ccs", 4)
1637  .Default(0);
1638  return RV;
1639 }
1640 
1642  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1643  switch (*Name) {
1644  default:
1645  return false;
1646  // Constant constraints.
1647  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1648  // instructions.
1649  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1650  // x86_64 instructions.
1651  case 's':
1652  Info.setRequiresImmediate();
1653  return true;
1654  case 'I':
1655  Info.setRequiresImmediate(0, 31);
1656  return true;
1657  case 'J':
1658  Info.setRequiresImmediate(0, 63);
1659  return true;
1660  case 'K':
1661  Info.setRequiresImmediate(-128, 127);
1662  return true;
1663  case 'L':
1664  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1665  return true;
1666  case 'M':
1667  Info.setRequiresImmediate(0, 3);
1668  return true;
1669  case 'N':
1670  Info.setRequiresImmediate(0, 255);
1671  return true;
1672  case 'O':
1673  Info.setRequiresImmediate(0, 127);
1674  return true;
1675  // Register constraints.
1676  case 'Y': // 'Y' is the first character for several 2-character constraints.
1677  // Shift the pointer to the second character of the constraint.
1678  Name++;
1679  switch (*Name) {
1680  default:
1681  return false;
1682  case 'z':
1683  case '0': // First SSE register.
1684  case '2':
1685  case 't': // Any SSE register, when SSE2 is enabled.
1686  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1687  case 'm': // Any MMX register, when inter-unit moves enabled.
1688  case 'k': // AVX512 arch mask registers: k1-k7.
1689  Info.setAllowsRegister();
1690  return true;
1691  }
1692  case 'f': // Any x87 floating point stack register.
1693  // Constraint 'f' cannot be used for output operands.
1694  if (Info.ConstraintStr[0] == '=')
1695  return false;
1696  Info.setAllowsRegister();
1697  return true;
1698  case 'a': // eax.
1699  case 'b': // ebx.
1700  case 'c': // ecx.
1701  case 'd': // edx.
1702  case 'S': // esi.
1703  case 'D': // edi.
1704  case 'A': // edx:eax.
1705  case 't': // Top of floating point stack.
1706  case 'u': // Second from top of floating point stack.
1707  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1708  case 'y': // Any MMX register.
1709  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1710  case 'x': // Any SSE register.
1711  case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1712  // for intermideate k reg operations).
1713  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1714  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1715  case 'l': // "Index" registers: any general register that can be used as an
1716  // index in a base+index memory access.
1717  Info.setAllowsRegister();
1718  return true;
1719  // Floating point constant constraints.
1720  case 'C': // SSE floating point constant.
1721  case 'G': // x87 floating point constant.
1722  return true;
1723  case '@':
1724  // CC condition changes.
1725  if (auto Len = matchAsmCCConstraint(Name)) {
1726  Name += Len - 1;
1727  Info.setAllowsRegister();
1728  return true;
1729  }
1730  return false;
1731  }
1732 }
1733 
1734 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1735  StringRef Constraint,
1736  unsigned Size) const {
1737  // Strip off constraint modifiers.
1738  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1739  Constraint = Constraint.substr(1);
1740 
1741  return validateOperandSize(FeatureMap, Constraint, Size);
1742 }
1743 
1744 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1745  StringRef Constraint,
1746  unsigned Size) const {
1747  return validateOperandSize(FeatureMap, Constraint, Size);
1748 }
1749 
1750 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1751  StringRef Constraint,
1752  unsigned Size) const {
1753  switch (Constraint[0]) {
1754  default:
1755  break;
1756  case 'k':
1757  // Registers k0-k7 (AVX512) size limit is 64 bit.
1758  case 'y':
1759  return Size <= 64;
1760  case 'f':
1761  case 't':
1762  case 'u':
1763  return Size <= 128;
1764  case 'Y':
1765  // 'Y' is the first character for several 2-character constraints.
1766  switch (Constraint[1]) {
1767  default:
1768  return false;
1769  case 'm':
1770  // 'Ym' is synonymous with 'y'.
1771  case 'k':
1772  return Size <= 64;
1773  case 'z':
1774  case '0':
1775  // XMM0
1776  if (FeatureMap.lookup("sse"))
1777  return Size <= 128U;
1778  return false;
1779  case 'i':
1780  case 't':
1781  case '2':
1782  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1783  if (SSELevel < SSE2)
1784  return false;
1785  break;
1786  }
1787  LLVM_FALLTHROUGH;
1788  case 'v':
1789  case 'x':
1790  if (FeatureMap.lookup("avx512f"))
1791  // 512-bit zmm registers can be used if target supports AVX512F.
1792  return Size <= 512U;
1793  else if (FeatureMap.lookup("avx"))
1794  // 256-bit ymm registers can be used if target supports AVX.
1795  return Size <= 256U;
1796  return Size <= 128U;
1797 
1798  }
1799 
1800  return true;
1801 }
1802 
1803 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1804  switch (*Constraint) {
1805  case '@':
1806  if (auto Len = matchAsmCCConstraint(Constraint)) {
1807  std::string Converted = "{" + std::string(Constraint, Len) + "}";
1808  Constraint += Len - 1;
1809  return Converted;
1810  }
1811  return std::string(1, *Constraint);
1812  case 'a':
1813  return std::string("{ax}");
1814  case 'b':
1815  return std::string("{bx}");
1816  case 'c':
1817  return std::string("{cx}");
1818  case 'd':
1819  return std::string("{dx}");
1820  case 'S':
1821  return std::string("{si}");
1822  case 'D':
1823  return std::string("{di}");
1824  case 'p': // address
1825  return std::string("im");
1826  case 't': // top of floating point stack.
1827  return std::string("{st}");
1828  case 'u': // second from top of floating point stack.
1829  return std::string("{st(1)}"); // second from top of floating point stack.
1830  case 'Y':
1831  switch (Constraint[1]) {
1832  default:
1833  // Break from inner switch and fall through (copy single char),
1834  // continue parsing after copying the current constraint into
1835  // the return string.
1836  break;
1837  case 'k':
1838  case 'm':
1839  case 'i':
1840  case 't':
1841  case 'z':
1842  case '0':
1843  case '2':
1844  // "^" hints llvm that this is a 2 letter constraint.
1845  // "Constraint++" is used to promote the string iterator
1846  // to the next constraint.
1847  return std::string("^") + std::string(Constraint++, 2);
1848  }
1849  LLVM_FALLTHROUGH;
1850  default:
1851  return std::string(1, *Constraint);
1852  }
1853 }
1854 
1856  // Perform any per-CPU checks necessary to determine if this CPU is
1857  // acceptable.
1858  switch (Kind) {
1859  case CK_Generic:
1860  // No processor selected!
1861  return false;
1862 #define PROC(ENUM, STRING, IS64BIT) \
1863  case CK_##ENUM: \
1864  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1865 #include "clang/Basic/X86Target.def"
1866  }
1867  llvm_unreachable("Unhandled CPU kind");
1868 }
1869 
1871 #define PROC(ENUM, STRING, IS64BIT) \
1872  if (IS64BIT || getTriple().getArch() == llvm::Triple::x86) \
1873  Values.emplace_back(STRING);
1874  // For aliases we need to lookup the CPUKind to check get the 64-bit ness.
1875 #define PROC_ALIAS(ENUM, ALIAS) \
1876  if (checkCPUKind(CK_##ENUM)) \
1877  Values.emplace_back(ALIAS);
1878 #include "clang/Basic/X86Target.def"
1879 }
1880 
1882  return llvm::StringSwitch<CPUKind>(CPU)
1883 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1884 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1885 #include "clang/Basic/X86Target.def"
1886  .Default(CK_Generic);
1887 }
1888 
1890  return llvm::makeArrayRef(GCCRegNames);
1891 }
1892 
1894  return llvm::makeArrayRef(AddlRegNames);
1895 }
1896 
1898  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1900 }
1901 
1903  return llvm::makeArrayRef(BuiltinInfoX86,
1905 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:54
bool validateOutputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1734
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:92
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:25
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:554
virtual bool validateOperandSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1750
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1300
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1893
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:897
void fillValidCPUList(SmallVectorImpl< StringRef > &Values) const override
Fill a SmallVectorImpl with the valid values to setCPU.
Definition: X86.cpp:1870
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:587
static unsigned matchAsmCCConstraint(const char *&Name)
Definition: X86.cpp:1607
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:67
__DEVICE__ int max(int __a, int __b)
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:53
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1508
void getCPUSpecificCPUDispatchFeatures(StringRef Name, llvm::SmallVectorImpl< StringRef > &Features) const override
Definition: X86.cpp:1582
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
Defines the Diagnostic-related interfaces.
static llvm::X86::ProcessorFeatures getFeature(StringRef Name)
Definition: X86.cpp:1515
#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME)
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1641
static const char *const GCCRegNames[]
Definition: X86.cpp:43
bool validateCPUSpecificCPUDispatch(StringRef Name) const override
Definition: X86.cpp:1560
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1336
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:402
static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name)
Definition: X86.cpp:1568
CPUKind getCPUKind(StringRef CPU) const
Definition: X86.cpp:1881
bool validateInputSize(const llvm::StringMap< bool > &FeatureMap, StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1744
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1418
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:471
Enumerates target-specific builtins in their own namespaces within namespace clang.
CPUKind
Enumeration of all of the X86 CPUs supported by Clang.
Definition: X86.h:133
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1902
Kind
static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat)
Definition: X86.cpp:1524
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1803
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1897
char CPUSpecificManglingCharacter(StringRef Name) const override
Definition: X86.cpp:1575
Dataflow Directional Tag Classes.
unsigned multiVersionSortPriority(StringRef Name) const override
Definition: X86.cpp:1539
#define CPU_SPECIFIC(NAME, MANGLING, FEATURES)
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:730
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:906
#define PROC(ENUM, STRING, IS64BIT)
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:106
bool checkCPUKind(CPUKind Kind) const
Definition: X86.cpp:1855
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:70
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:29
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:622
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1596
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1889
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:104