clang  10.0.0git
PPC.h
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1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares PPC TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
14 #define LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
15 
16 #include "OSTargets.h"
17 #include "clang/Basic/TargetInfo.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/Support/Compiler.h"
22 
23 namespace clang {
24 namespace targets {
25 
26 // PPC abstract base class
27 class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
28 
29  /// Flags for architecture specific defines.
30  typedef enum {
31  ArchDefineNone = 0,
32  ArchDefineName = 1 << 0, // <name> is substituted for arch name.
33  ArchDefinePpcgr = 1 << 1,
34  ArchDefinePpcsq = 1 << 2,
35  ArchDefine440 = 1 << 3,
36  ArchDefine603 = 1 << 4,
37  ArchDefine604 = 1 << 5,
38  ArchDefinePwr4 = 1 << 6,
39  ArchDefinePwr5 = 1 << 7,
40  ArchDefinePwr5x = 1 << 8,
41  ArchDefinePwr6 = 1 << 9,
42  ArchDefinePwr6x = 1 << 10,
43  ArchDefinePwr7 = 1 << 11,
44  ArchDefinePwr8 = 1 << 12,
45  ArchDefinePwr9 = 1 << 13,
46  ArchDefineFuture = 1 << 14,
47  ArchDefineA2 = 1 << 15,
48  ArchDefineA2q = 1 << 16,
49  ArchDefineE500 = 1 << 17
50  } ArchDefineTypes;
51 
52 
53  ArchDefineTypes ArchDefs = ArchDefineNone;
54  static const Builtin::Info BuiltinInfo[];
55  static const char *const GCCRegNames[];
56  static const TargetInfo::GCCRegAlias GCCRegAliases[];
57  std::string CPU;
58  enum PPCFloatABI { HardFloat, SoftFloat } FloatABI;
59 
60  // Target cpu features.
61  bool HasAltivec = false;
62  bool HasVSX = false;
63  bool HasP8Vector = false;
64  bool HasP8Crypto = false;
65  bool HasDirectMove = false;
66  bool HasQPX = false;
67  bool HasHTM = false;
68  bool HasBPERMD = false;
69  bool HasExtDiv = false;
70  bool HasP9Vector = false;
71  bool HasSPE = false;
72 
73 protected:
74  std::string ABI;
75 
76 public:
77  PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
78  : TargetInfo(Triple) {
79  SuitableAlign = 128;
80  SimdDefaultAlign = 128;
81  LongDoubleWidth = LongDoubleAlign = 128;
82  LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble();
83  }
84 
85  // Set the language option for altivec based on our value.
86  void adjust(LangOptions &Opts) override;
87 
88  // Note: GCC recognizes the following additional cpus:
89  // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
90  // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
91  bool isValidCPUName(StringRef Name) const override;
92  void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
93 
94  bool setCPU(const std::string &Name) override {
95  bool CPUKnown = isValidCPUName(Name);
96  if (CPUKnown) {
97  CPU = Name;
98 
99  // CPU identification.
100  ArchDefs =
101  (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
102  .Case("440", ArchDefineName)
103  .Case("450", ArchDefineName | ArchDefine440)
104  .Case("601", ArchDefineName)
105  .Case("602", ArchDefineName | ArchDefinePpcgr)
106  .Case("603", ArchDefineName | ArchDefinePpcgr)
107  .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
108  .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
109  .Case("604", ArchDefineName | ArchDefinePpcgr)
110  .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
111  .Case("620", ArchDefineName | ArchDefinePpcgr)
112  .Case("630", ArchDefineName | ArchDefinePpcgr)
113  .Case("7400", ArchDefineName | ArchDefinePpcgr)
114  .Case("7450", ArchDefineName | ArchDefinePpcgr)
115  .Case("750", ArchDefineName | ArchDefinePpcgr)
116  .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
117  ArchDefinePpcsq)
118  .Case("a2", ArchDefineA2)
119  .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q)
120  .Cases("power3", "pwr3", ArchDefinePpcgr)
121  .Cases("power4", "pwr4",
122  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
123  .Cases("power5", "pwr5",
124  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
125  ArchDefinePpcsq)
126  .Cases("power5x", "pwr5x",
127  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
128  ArchDefinePpcgr | ArchDefinePpcsq)
129  .Cases("power6", "pwr6",
130  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
131  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
132  .Cases("power6x", "pwr6x",
133  ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x |
134  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
135  ArchDefinePpcsq)
136  .Cases("power7", "pwr7",
137  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
138  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
139  ArchDefinePpcsq)
140  // powerpc64le automatically defaults to at least power8.
141  .Cases("power8", "pwr8", "ppc64le",
142  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
143  ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
144  ArchDefinePpcgr | ArchDefinePpcsq)
145  .Cases("power9", "pwr9",
146  ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
147  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
148  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
149  .Case("future",
150  ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 |
151  ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
152  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
153  ArchDefinePpcsq)
154  .Cases("8548", "e500", ArchDefineE500)
155  .Default(ArchDefineNone);
156  }
157  return CPUKnown;
158  }
159 
160  StringRef getABI() const override { return ABI; }
161 
162  ArrayRef<Builtin::Info> getTargetBuiltins() const override;
163 
164  bool isCLZForZeroUndef() const override { return false; }
165 
166  void getTargetDefines(const LangOptions &Opts,
167  MacroBuilder &Builder) const override;
168 
169  bool
170  initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
171  StringRef CPU,
172  const std::vector<std::string> &FeaturesVec) const override;
173 
174  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
175 
176  bool handleTargetFeatures(std::vector<std::string> &Features,
177  DiagnosticsEngine &Diags) override;
178 
179  bool hasFeature(StringRef Feature) const override;
180 
181  void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
182  bool Enabled) const override;
183 
184  ArrayRef<const char *> getGCCRegNames() const override;
185 
186  ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
187 
188  ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
189 
190  bool validateAsmConstraint(const char *&Name,
191  TargetInfo::ConstraintInfo &Info) const override {
192  switch (*Name) {
193  default:
194  return false;
195  case 'O': // Zero
196  break;
197  case 'f': // Floating point register
198  // Don't use floating point registers on soft float ABI.
199  if (FloatABI == SoftFloat)
200  return false;
201  LLVM_FALLTHROUGH;
202  case 'b': // Base register
203  Info.setAllowsRegister();
204  break;
205  // FIXME: The following are added to allow parsing.
206  // I just took a guess at what the actions should be.
207  // Also, is more specific checking needed? I.e. specific registers?
208  case 'd': // Floating point register (containing 64-bit value)
209  case 'v': // Altivec vector register
210  // Don't use floating point and altivec vector registers
211  // on soft float ABI
212  if (FloatABI == SoftFloat)
213  return false;
214  Info.setAllowsRegister();
215  break;
216  case 'w':
217  switch (Name[1]) {
218  case 'd': // VSX vector register to hold vector double data
219  case 'f': // VSX vector register to hold vector float data
220  case 's': // VSX vector register to hold scalar double data
221  case 'w': // VSX vector register to hold scalar double data
222  case 'a': // Any VSX register
223  case 'c': // An individual CR bit
224  case 'i': // FP or VSX register to hold 64-bit integers data
225  break;
226  default:
227  return false;
228  }
229  Info.setAllowsRegister();
230  Name++; // Skip over 'w'.
231  break;
232  case 'h': // `MQ', `CTR', or `LINK' register
233  case 'q': // `MQ' register
234  case 'c': // `CTR' register
235  case 'l': // `LINK' register
236  case 'x': // `CR' register (condition register) number 0
237  case 'y': // `CR' register (condition register)
238  case 'z': // `XER[CA]' carry bit (part of the XER register)
239  Info.setAllowsRegister();
240  break;
241  case 'I': // Signed 16-bit constant
242  case 'J': // Unsigned 16-bit constant shifted left 16 bits
243  // (use `L' instead for SImode constants)
244  case 'K': // Unsigned 16-bit constant
245  case 'L': // Signed 16-bit constant shifted left 16 bits
246  case 'M': // Constant larger than 31
247  case 'N': // Exact power of 2
248  case 'P': // Constant whose negation is a signed 16-bit constant
249  case 'G': // Floating point constant that can be loaded into a
250  // register with one instruction per word
251  case 'H': // Integer/Floating point constant that can be loaded
252  // into a register using three instructions
253  break;
254  case 'm': // Memory operand. Note that on PowerPC targets, m can
255  // include addresses that update the base register. It
256  // is therefore only safe to use `m' in an asm statement
257  // if that asm statement accesses the operand exactly once.
258  // The asm statement must also use `%U<opno>' as a
259  // placeholder for the "update" flag in the corresponding
260  // load or store instruction. For example:
261  // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
262  // is correct but:
263  // asm ("st %1,%0" : "=m" (mem) : "r" (val));
264  // is not. Use es rather than m if you don't want the base
265  // register to be updated.
266  case 'e':
267  if (Name[1] != 's')
268  return false;
269  // es: A "stable" memory operand; that is, one which does not
270  // include any automodification of the base register. Unlike
271  // `m', this constraint can be used in asm statements that
272  // might access the operand several times, or that might not
273  // access it at all.
274  Info.setAllowsMemory();
275  Name++; // Skip over 'e'.
276  break;
277  case 'Q': // Memory operand that is an offset from a register (it is
278  // usually better to use `m' or `es' in asm statements)
279  case 'Z': // Memory operand that is an indexed or indirect from a
280  // register (it is usually better to use `m' or `es' in
281  // asm statements)
282  Info.setAllowsMemory();
283  Info.setAllowsRegister();
284  break;
285  case 'R': // AIX TOC entry
286  case 'a': // Address operand that is an indexed or indirect from a
287  // register (`p' is preferable for asm statements)
288  case 'S': // Constant suitable as a 64-bit mask operand
289  case 'T': // Constant suitable as a 32-bit mask operand
290  case 'U': // System V Release 4 small data area reference
291  case 't': // AND masks that can be performed by two rldic{l, r}
292  // instructions
293  case 'W': // Vector constant that does not require memory
294  case 'j': // Vector constant that is all zeros.
295  break;
296  // End FIXME.
297  }
298  return true;
299  }
300 
301  std::string convertConstraint(const char *&Constraint) const override {
302  std::string R;
303  switch (*Constraint) {
304  case 'e':
305  case 'w':
306  // Two-character constraint; add "^" hint for later parsing.
307  R = std::string("^") + std::string(Constraint, 2);
308  Constraint++;
309  break;
310  default:
311  return TargetInfo::convertConstraint(Constraint);
312  }
313  return R;
314  }
315 
316  const char *getClobbers() const override { return ""; }
317  int getEHDataRegisterNumber(unsigned RegNo) const override {
318  if (RegNo == 0)
319  return 3;
320  if (RegNo == 1)
321  return 4;
322  return -1;
323  }
324 
325  bool hasSjLjLowering() const override { return true; }
326 
327  const char *getLongDoubleMangling() const override {
328  if (LongDoubleWidth == 64)
329  return "e";
330  return LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble()
331  ? "g"
332  : "u9__ieee128";
333  }
334  const char *getFloat128Mangling() const override { return "u9__ieee128"; }
335 };
336 
337 class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
338 public:
339  PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
340  : PPCTargetInfo(Triple, Opts) {
341  resetDataLayout("E-m:e-p:32:32-i64:64-n32");
342 
343  switch (getTriple().getOS()) {
344  case llvm::Triple::Linux:
345  case llvm::Triple::FreeBSD:
346  case llvm::Triple::NetBSD:
347  SizeType = UnsignedInt;
348  PtrDiffType = SignedInt;
349  IntPtrType = SignedInt;
350  break;
351  case llvm::Triple::AIX:
352  SizeType = UnsignedLong;
353  PtrDiffType = SignedLong;
354  IntPtrType = SignedLong;
355  SuitableAlign = 64;
356  break;
357  default:
358  break;
359  }
360 
361  if (Triple.isOSFreeBSD() || Triple.isOSNetBSD() || Triple.isOSOpenBSD() ||
362  Triple.getOS() == llvm::Triple::AIX || Triple.isMusl()) {
363  LongDoubleWidth = LongDoubleAlign = 64;
364  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
365  }
366 
367  // PPC32 supports atomics up to 4 bytes.
368  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
369  }
370 
372  // This is the ELF definition, and is overridden by the Darwin sub-target
374  }
375 };
376 
377 // Note: ABI differences may eventually require us to have a separate
378 // TargetInfo for little endian.
379 class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
380 public:
381  PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
382  : PPCTargetInfo(Triple, Opts) {
383  LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
384  IntMaxType = SignedLong;
385  Int64Type = SignedLong;
386 
387  if ((Triple.getArch() == llvm::Triple::ppc64le)) {
388  resetDataLayout("e-m:e-i64:64-n32:64");
389  ABI = "elfv2";
390  } else {
391  resetDataLayout("E-m:e-i64:64-n32:64");
392  ABI = "elfv1";
393  }
394 
395  if (Triple.getOS() == llvm::Triple::AIX)
396  SuitableAlign = 64;
397 
398  if (Triple.isOSFreeBSD() || Triple.getOS() == llvm::Triple::AIX ||
399  Triple.isMusl()) {
400  LongDoubleWidth = LongDoubleAlign = 64;
401  LongDoubleFormat = &llvm::APFloat::IEEEdouble();
402  }
403 
404  // PPC64 supports atomics up to 8 bytes.
405  MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
406  }
407 
410  }
411 
412  // PPC64 Linux-specific ABI options.
413  bool setABI(const std::string &Name) override {
414  if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
415  ABI = Name;
416  return true;
417  }
418  return false;
419  }
420 
422  switch (CC) {
423  case CC_Swift:
424  return CCCR_OK;
425  default:
426  return CCCR_Warning;
427  }
428  }
429 };
430 
431 class LLVM_LIBRARY_VISIBILITY DarwinPPC32TargetInfo
432  : public DarwinTargetInfo<PPC32TargetInfo> {
433 public:
434  DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
435  : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) {
436  HasAlignMac68kSupport = true;
437  BoolWidth = BoolAlign = 32; // XXX support -mone-byte-bool?
438  PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
439  LongLongAlign = 32;
440  resetDataLayout("E-m:o-p:32:32-f64:32:64-n32");
441  }
442 
445  }
446 };
447 
448 class LLVM_LIBRARY_VISIBILITY DarwinPPC64TargetInfo
449  : public DarwinTargetInfo<PPC64TargetInfo> {
450 public:
451  DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
452  : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) {
453  HasAlignMac68kSupport = true;
454  resetDataLayout("E-m:o-i64:64-n32:64");
455  }
456 };
457 
458 class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo :
459  public AIXTargetInfo<PPC32TargetInfo> {
460 public:
464  }
465 };
466 
467 class LLVM_LIBRARY_VISIBILITY AIXPPC64TargetInfo :
468  public AIXTargetInfo<PPC64TargetInfo> {
469 public:
471 };
472 
473 } // namespace targets
474 } // namespace clang
475 #endif // LLVM_CLANG_LIB_BASIC_TARGETS_PPC_H
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:339
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override
Determines whether a given calling convention is valid for the target.
Definition: PPC.h:421
DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:451
static const Builtin::Info BuiltinInfo[]
Definition: Builtins.cpp:20
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:371
Options for controlling the target.
Definition: TargetOptions.h:26
PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:381
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:53
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:149
StringRef getABI() const override
Get the ABI currently in use.
Definition: PPC.h:160
static const char *const GCCRegNames[]
Definition: X86.cpp:43
AIXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: OSTargets.h:707
DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
Definition: PPC.h:434
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:408
Exposes information about the current target.
Definition: TargetInfo.h:164
bool setABI(const std::string &Name) override
Use the specified ABI.
Definition: PPC.h:413
bool setCPU(const std::string &Name) override
Target the specified CPU.
Definition: PPC.h:94
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:265
int getEHDataRegisterNumber(unsigned RegNo) const override
Return the register number that __builtin_eh_return_regno would return with the specified argument...
Definition: PPC.h:317
Defines the clang::TargetOptions class.
__builtin_va_list as defined by the Power ABI: https://www.power.org /resources/downloads/Power-Arch-...
Definition: TargetInfo.h:244
const char * getFloat128Mangling() const override
Return the mangled code of __float128.
Definition: PPC.h:334
bool isCLZForZeroUndef() const override
The __builtin_clz* and __builtin_ctz* built-in functions are specified to have undefined results for ...
Definition: PPC.h:164
Dataflow Directional Tag Classes.
typedef char* __builtin_va_list;
Definition: TargetInfo.h:228
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:462
clang::driver::toolchains::AIX AIX
Definition: AIX.cpp:17
BuiltinVaListKind
The different kinds of __builtin_va_list types defined by the target implementation.
Definition: TargetInfo.h:226
bool hasSjLjLowering() const override
Controls if __builtin_longjmp / __builtin_setjmp can be lowered to llvm.eh.sjlj.longjmp / llvm...
Definition: PPC.h:325
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:106
Defines the clang::TargetInfo interface.
BuiltinVaListKind getBuiltinVaListKind() const override
Returns the kind of __builtin_va_list type that should be used with this target.
Definition: PPC.h:443
PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
Definition: PPC.h:77
std::string convertConstraint(const char *&Constraint) const override
Definition: PPC.h:301
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override
Definition: PPC.h:190
const char * getClobbers() const override
Returns a string of target-specific clobbers, in LLVM format.
Definition: PPC.h:316
virtual std::string convertConstraint(const char *&Constraint) const
Definition: TargetInfo.h:977
const char * getLongDoubleMangling() const override
Return the mangled code of long double.
Definition: PPC.h:327