clang  6.0.0
X86.cpp
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1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements X86 TargetInfo objects.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "X86.h"
15 #include "clang/Basic/Builtins.h"
16 #include "clang/Basic/Diagnostic.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 
21 namespace clang {
22 namespace targets {
23 
25 #define BUILTIN(ID, TYPE, ATTRS) \
26  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
27 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
28  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
29 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
30  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
31 #include "clang/Basic/BuiltinsX86.def"
32 
33 #define BUILTIN(ID, TYPE, ATTRS) \
34  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
35 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
36  {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
37 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \
38  {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
39 #include "clang/Basic/BuiltinsX86_64.def"
40 };
41 
42 static const char *const GCCRegNames[] = {
43  "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
44  "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
45  "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", "xmm0", "xmm1",
46  "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "mm0", "mm1",
47  "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "r8", "r9",
48  "r10", "r11", "r12", "r13", "r14", "r15", "xmm8", "xmm9",
49  "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "ymm0", "ymm1",
50  "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9",
51  "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "xmm16", "xmm17",
52  "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25",
53  "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm16", "ymm17",
54  "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25",
55  "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1",
56  "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9",
57  "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17",
58  "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25",
59  "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "k0", "k1",
60  "k2", "k3", "k4", "k5", "k6", "k7",
61  "cr0", "cr2", "cr3", "cr4", "cr8",
62  "dr0", "dr1", "dr2", "dr3", "dr6", "dr7",
63  "bnd0", "bnd1", "bnd2", "bnd3",
64 };
65 
67  {{"al", "ah", "eax", "rax"}, 0},
68  {{"bl", "bh", "ebx", "rbx"}, 3},
69  {{"cl", "ch", "ecx", "rcx"}, 2},
70  {{"dl", "dh", "edx", "rdx"}, 1},
71  {{"esi", "rsi"}, 4},
72  {{"edi", "rdi"}, 5},
73  {{"esp", "rsp"}, 7},
74  {{"ebp", "rbp"}, 6},
75  {{"r8d", "r8w", "r8b"}, 38},
76  {{"r9d", "r9w", "r9b"}, 39},
77  {{"r10d", "r10w", "r10b"}, 40},
78  {{"r11d", "r11w", "r11b"}, 41},
79  {{"r12d", "r12w", "r12b"}, 42},
80  {{"r13d", "r13w", "r13b"}, 43},
81  {{"r14d", "r14w", "r14b"}, 44},
82  {{"r15d", "r15w", "r15b"}, 45},
83 };
84 
85 } // namespace targets
86 } // namespace clang
87 
88 using namespace clang;
89 using namespace clang::targets;
90 
91 bool X86TargetInfo::setFPMath(StringRef Name) {
92  if (Name == "387") {
93  FPMath = FP_387;
94  return true;
95  }
96  if (Name == "sse") {
97  FPMath = FP_SSE;
98  return true;
99  }
100  return false;
101 }
102 
104  llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
105  const std::vector<std::string> &FeaturesVec) const {
106  // FIXME: This *really* should not be here.
107  // X86_64 always has SSE2.
108  if (getTriple().getArch() == llvm::Triple::x86_64)
109  setFeatureEnabledImpl(Features, "sse2", true);
110 
111  const CPUKind Kind = getCPUKind(CPU);
112 
113  // Enable X87 for all X86 processors but Lakemont.
114  if (Kind != CK_Lakemont)
115  setFeatureEnabledImpl(Features, "x87", true);
116 
117  switch (Kind) {
118  case CK_Generic:
119  case CK_i386:
120  case CK_i486:
121  case CK_i586:
122  case CK_Pentium:
123  case CK_PentiumPro:
124  case CK_Lakemont:
125  break;
126 
127  case CK_PentiumMMX:
128  case CK_Pentium2:
129  case CK_K6:
130  case CK_WinChipC6:
131  setFeatureEnabledImpl(Features, "mmx", true);
132  break;
133 
134  case CK_Icelake:
135  setFeatureEnabledImpl(Features, "vaes", true);
136  setFeatureEnabledImpl(Features, "gfni", true);
137  setFeatureEnabledImpl(Features, "vpclmulqdq", true);
138  setFeatureEnabledImpl(Features, "avx512bitalg", true);
139  setFeatureEnabledImpl(Features, "avx512vnni", true);
140  setFeatureEnabledImpl(Features, "avx512vbmi2", true);
141  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
142  LLVM_FALLTHROUGH;
143  case CK_Cannonlake:
144  setFeatureEnabledImpl(Features, "avx512ifma", true);
145  setFeatureEnabledImpl(Features, "avx512vbmi", true);
146  setFeatureEnabledImpl(Features, "sha", true);
147  LLVM_FALLTHROUGH;
148  case CK_SkylakeServer:
149  setFeatureEnabledImpl(Features, "avx512f", true);
150  setFeatureEnabledImpl(Features, "avx512cd", true);
151  setFeatureEnabledImpl(Features, "avx512dq", true);
152  setFeatureEnabledImpl(Features, "avx512bw", true);
153  setFeatureEnabledImpl(Features, "avx512vl", true);
154  setFeatureEnabledImpl(Features, "pku", true);
155  if (Kind != CK_Cannonlake) // CNL inherits all SKX features, except CLWB
156  setFeatureEnabledImpl(Features, "clwb", true);
157  LLVM_FALLTHROUGH;
158  case CK_SkylakeClient:
159  setFeatureEnabledImpl(Features, "xsavec", true);
160  setFeatureEnabledImpl(Features, "xsaves", true);
161  setFeatureEnabledImpl(Features, "mpx", true);
162  setFeatureEnabledImpl(Features, "sgx", true);
163  setFeatureEnabledImpl(Features, "clflushopt", true);
164  setFeatureEnabledImpl(Features, "rtm", true);
165  LLVM_FALLTHROUGH;
166  case CK_Broadwell:
167  setFeatureEnabledImpl(Features, "rdseed", true);
168  setFeatureEnabledImpl(Features, "adx", true);
169  setFeatureEnabledImpl(Features, "prfchw", true);
170  LLVM_FALLTHROUGH;
171  case CK_Haswell:
172  setFeatureEnabledImpl(Features, "avx2", true);
173  setFeatureEnabledImpl(Features, "lzcnt", true);
174  setFeatureEnabledImpl(Features, "bmi", true);
175  setFeatureEnabledImpl(Features, "bmi2", true);
176  setFeatureEnabledImpl(Features, "fma", true);
177  setFeatureEnabledImpl(Features, "movbe", true);
178  LLVM_FALLTHROUGH;
179  case CK_IvyBridge:
180  setFeatureEnabledImpl(Features, "rdrnd", true);
181  setFeatureEnabledImpl(Features, "f16c", true);
182  setFeatureEnabledImpl(Features, "fsgsbase", true);
183  LLVM_FALLTHROUGH;
184  case CK_SandyBridge:
185  setFeatureEnabledImpl(Features, "avx", true);
186  setFeatureEnabledImpl(Features, "xsave", true);
187  setFeatureEnabledImpl(Features, "xsaveopt", true);
188  LLVM_FALLTHROUGH;
189  case CK_Westmere:
190  setFeatureEnabledImpl(Features, "aes", true);
191  setFeatureEnabledImpl(Features, "pclmul", true);
192  LLVM_FALLTHROUGH;
193  case CK_Nehalem:
194  setFeatureEnabledImpl(Features, "sse4.2", true);
195  LLVM_FALLTHROUGH;
196  case CK_Penryn:
197  setFeatureEnabledImpl(Features, "sse4.1", true);
198  LLVM_FALLTHROUGH;
199  case CK_Core2:
200  setFeatureEnabledImpl(Features, "ssse3", true);
201  LLVM_FALLTHROUGH;
202  case CK_Yonah:
203  case CK_Prescott:
204  case CK_Nocona:
205  setFeatureEnabledImpl(Features, "sse3", true);
206  setFeatureEnabledImpl(Features, "cx16", true);
207  LLVM_FALLTHROUGH;
208  case CK_PentiumM:
209  case CK_Pentium4:
210  case CK_x86_64:
211  setFeatureEnabledImpl(Features, "sse2", true);
212  LLVM_FALLTHROUGH;
213  case CK_Pentium3:
214  case CK_C3_2:
215  setFeatureEnabledImpl(Features, "sse", true);
216  setFeatureEnabledImpl(Features, "fxsr", true);
217  break;
218 
219  case CK_Goldmont:
220  setFeatureEnabledImpl(Features, "sha", true);
221  setFeatureEnabledImpl(Features, "rdrnd", true);
222  setFeatureEnabledImpl(Features, "rdseed", true);
223  setFeatureEnabledImpl(Features, "xsave", true);
224  setFeatureEnabledImpl(Features, "xsaveopt", true);
225  setFeatureEnabledImpl(Features, "xsavec", true);
226  setFeatureEnabledImpl(Features, "xsaves", true);
227  setFeatureEnabledImpl(Features, "clflushopt", true);
228  setFeatureEnabledImpl(Features, "mpx", true);
229  setFeatureEnabledImpl(Features, "fsgsbase", true);
230  LLVM_FALLTHROUGH;
231  case CK_Silvermont:
232  setFeatureEnabledImpl(Features, "aes", true);
233  setFeatureEnabledImpl(Features, "pclmul", true);
234  setFeatureEnabledImpl(Features, "sse4.2", true);
235  setFeatureEnabledImpl(Features, "prfchw", true);
236  LLVM_FALLTHROUGH;
237  case CK_Bonnell:
238  setFeatureEnabledImpl(Features, "movbe", true);
239  setFeatureEnabledImpl(Features, "ssse3", true);
240  setFeatureEnabledImpl(Features, "fxsr", true);
241  setFeatureEnabledImpl(Features, "cx16", true);
242  break;
243 
244  case CK_KNM:
245  // TODO: Add avx5124fmaps/avx5124vnniw.
246  setFeatureEnabledImpl(Features, "avx512vpopcntdq", true);
247  LLVM_FALLTHROUGH;
248  case CK_KNL:
249  setFeatureEnabledImpl(Features, "avx512f", true);
250  setFeatureEnabledImpl(Features, "avx512cd", true);
251  setFeatureEnabledImpl(Features, "avx512er", true);
252  setFeatureEnabledImpl(Features, "avx512pf", true);
253  setFeatureEnabledImpl(Features, "prfchw", true);
254  setFeatureEnabledImpl(Features, "prefetchwt1", true);
255  setFeatureEnabledImpl(Features, "fxsr", true);
256  setFeatureEnabledImpl(Features, "rdseed", true);
257  setFeatureEnabledImpl(Features, "adx", true);
258  setFeatureEnabledImpl(Features, "lzcnt", true);
259  setFeatureEnabledImpl(Features, "bmi", true);
260  setFeatureEnabledImpl(Features, "bmi2", true);
261  setFeatureEnabledImpl(Features, "rtm", true);
262  setFeatureEnabledImpl(Features, "fma", true);
263  setFeatureEnabledImpl(Features, "rdrnd", true);
264  setFeatureEnabledImpl(Features, "f16c", true);
265  setFeatureEnabledImpl(Features, "fsgsbase", true);
266  setFeatureEnabledImpl(Features, "aes", true);
267  setFeatureEnabledImpl(Features, "pclmul", true);
268  setFeatureEnabledImpl(Features, "cx16", true);
269  setFeatureEnabledImpl(Features, "xsaveopt", true);
270  setFeatureEnabledImpl(Features, "xsave", true);
271  setFeatureEnabledImpl(Features, "movbe", true);
272  break;
273 
274  case CK_K6_2:
275  case CK_K6_3:
276  case CK_WinChip2:
277  case CK_C3:
278  setFeatureEnabledImpl(Features, "3dnow", true);
279  break;
280 
281  case CK_AMDFAM10:
282  setFeatureEnabledImpl(Features, "sse4a", true);
283  setFeatureEnabledImpl(Features, "lzcnt", true);
284  setFeatureEnabledImpl(Features, "popcnt", true);
285  LLVM_FALLTHROUGH;
286  case CK_K8SSE3:
287  setFeatureEnabledImpl(Features, "sse3", true);
288  LLVM_FALLTHROUGH;
289  case CK_K8:
290  setFeatureEnabledImpl(Features, "sse2", true);
291  LLVM_FALLTHROUGH;
292  case CK_AthlonXP:
293  setFeatureEnabledImpl(Features, "sse", true);
294  setFeatureEnabledImpl(Features, "fxsr", true);
295  LLVM_FALLTHROUGH;
296  case CK_Athlon:
297  case CK_Geode:
298  setFeatureEnabledImpl(Features, "3dnowa", true);
299  break;
300 
301  case CK_BTVER2:
302  setFeatureEnabledImpl(Features, "avx", true);
303  setFeatureEnabledImpl(Features, "aes", true);
304  setFeatureEnabledImpl(Features, "pclmul", true);
305  setFeatureEnabledImpl(Features, "bmi", true);
306  setFeatureEnabledImpl(Features, "f16c", true);
307  setFeatureEnabledImpl(Features, "xsaveopt", true);
308  setFeatureEnabledImpl(Features, "movbe", true);
309  LLVM_FALLTHROUGH;
310  case CK_BTVER1:
311  setFeatureEnabledImpl(Features, "ssse3", true);
312  setFeatureEnabledImpl(Features, "sse4a", true);
313  setFeatureEnabledImpl(Features, "lzcnt", true);
314  setFeatureEnabledImpl(Features, "popcnt", true);
315  setFeatureEnabledImpl(Features, "prfchw", true);
316  setFeatureEnabledImpl(Features, "cx16", true);
317  setFeatureEnabledImpl(Features, "fxsr", true);
318  break;
319 
320  case CK_ZNVER1:
321  setFeatureEnabledImpl(Features, "adx", true);
322  setFeatureEnabledImpl(Features, "aes", true);
323  setFeatureEnabledImpl(Features, "avx2", true);
324  setFeatureEnabledImpl(Features, "bmi", true);
325  setFeatureEnabledImpl(Features, "bmi2", true);
326  setFeatureEnabledImpl(Features, "clflushopt", true);
327  setFeatureEnabledImpl(Features, "clzero", true);
328  setFeatureEnabledImpl(Features, "cx16", true);
329  setFeatureEnabledImpl(Features, "f16c", true);
330  setFeatureEnabledImpl(Features, "fma", true);
331  setFeatureEnabledImpl(Features, "fsgsbase", true);
332  setFeatureEnabledImpl(Features, "fxsr", true);
333  setFeatureEnabledImpl(Features, "lzcnt", true);
334  setFeatureEnabledImpl(Features, "mwaitx", true);
335  setFeatureEnabledImpl(Features, "movbe", true);
336  setFeatureEnabledImpl(Features, "pclmul", true);
337  setFeatureEnabledImpl(Features, "popcnt", true);
338  setFeatureEnabledImpl(Features, "prfchw", true);
339  setFeatureEnabledImpl(Features, "rdrnd", true);
340  setFeatureEnabledImpl(Features, "rdseed", true);
341  setFeatureEnabledImpl(Features, "sha", true);
342  setFeatureEnabledImpl(Features, "sse4a", true);
343  setFeatureEnabledImpl(Features, "xsave", true);
344  setFeatureEnabledImpl(Features, "xsavec", true);
345  setFeatureEnabledImpl(Features, "xsaveopt", true);
346  setFeatureEnabledImpl(Features, "xsaves", true);
347  break;
348 
349  case CK_BDVER4:
350  setFeatureEnabledImpl(Features, "avx2", true);
351  setFeatureEnabledImpl(Features, "bmi2", true);
352  setFeatureEnabledImpl(Features, "mwaitx", true);
353  LLVM_FALLTHROUGH;
354  case CK_BDVER3:
355  setFeatureEnabledImpl(Features, "fsgsbase", true);
356  setFeatureEnabledImpl(Features, "xsaveopt", true);
357  LLVM_FALLTHROUGH;
358  case CK_BDVER2:
359  setFeatureEnabledImpl(Features, "bmi", true);
360  setFeatureEnabledImpl(Features, "fma", true);
361  setFeatureEnabledImpl(Features, "f16c", true);
362  setFeatureEnabledImpl(Features, "tbm", true);
363  LLVM_FALLTHROUGH;
364  case CK_BDVER1:
365  // xop implies avx, sse4a and fma4.
366  setFeatureEnabledImpl(Features, "xop", true);
367  setFeatureEnabledImpl(Features, "lwp", true);
368  setFeatureEnabledImpl(Features, "lzcnt", true);
369  setFeatureEnabledImpl(Features, "aes", true);
370  setFeatureEnabledImpl(Features, "pclmul", true);
371  setFeatureEnabledImpl(Features, "prfchw", true);
372  setFeatureEnabledImpl(Features, "cx16", true);
373  setFeatureEnabledImpl(Features, "fxsr", true);
374  setFeatureEnabledImpl(Features, "xsave", true);
375  break;
376  }
377  if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
378  return false;
379 
380  // Can't do this earlier because we need to be able to explicitly enable
381  // or disable these features and the things that they depend upon.
382 
383  // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
384  auto I = Features.find("sse4.2");
385  if (I != Features.end() && I->getValue() &&
386  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
387  FeaturesVec.end())
388  Features["popcnt"] = true;
389 
390  // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
391  I = Features.find("3dnow");
392  if (I != Features.end() && I->getValue() &&
393  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
394  FeaturesVec.end())
395  Features["prfchw"] = true;
396 
397  // Additionally, if SSE is enabled and mmx is not explicitly disabled,
398  // then enable MMX.
399  I = Features.find("sse");
400  if (I != Features.end() && I->getValue() &&
401  std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
402  FeaturesVec.end())
403  Features["mmx"] = true;
404 
405  return true;
406 }
407 
408 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
409  X86SSEEnum Level, bool Enabled) {
410  if (Enabled) {
411  switch (Level) {
412  case AVX512F:
413  Features["avx512f"] = Features["fma"] = Features["f16c"] = true;
414  LLVM_FALLTHROUGH;
415  case AVX2:
416  Features["avx2"] = true;
417  LLVM_FALLTHROUGH;
418  case AVX:
419  Features["avx"] = true;
420  Features["xsave"] = true;
421  LLVM_FALLTHROUGH;
422  case SSE42:
423  Features["sse4.2"] = true;
424  LLVM_FALLTHROUGH;
425  case SSE41:
426  Features["sse4.1"] = true;
427  LLVM_FALLTHROUGH;
428  case SSSE3:
429  Features["ssse3"] = true;
430  LLVM_FALLTHROUGH;
431  case SSE3:
432  Features["sse3"] = true;
433  LLVM_FALLTHROUGH;
434  case SSE2:
435  Features["sse2"] = true;
436  LLVM_FALLTHROUGH;
437  case SSE1:
438  Features["sse"] = true;
439  LLVM_FALLTHROUGH;
440  case NoSSE:
441  break;
442  }
443  return;
444  }
445 
446  switch (Level) {
447  case NoSSE:
448  case SSE1:
449  Features["sse"] = false;
450  LLVM_FALLTHROUGH;
451  case SSE2:
452  Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
453  Features["gfni"] = false;
454  LLVM_FALLTHROUGH;
455  case SSE3:
456  Features["sse3"] = false;
457  setXOPLevel(Features, NoXOP, false);
458  LLVM_FALLTHROUGH;
459  case SSSE3:
460  Features["ssse3"] = false;
461  LLVM_FALLTHROUGH;
462  case SSE41:
463  Features["sse4.1"] = false;
464  LLVM_FALLTHROUGH;
465  case SSE42:
466  Features["sse4.2"] = false;
467  LLVM_FALLTHROUGH;
468  case AVX:
469  Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
470  Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = false;
471  setXOPLevel(Features, FMA4, false);
472  LLVM_FALLTHROUGH;
473  case AVX2:
474  Features["avx2"] = false;
475  LLVM_FALLTHROUGH;
476  case AVX512F:
477  Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
478  Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
479  Features["avx512vl"] = Features["avx512vbmi"] =
480  Features["avx512ifma"] = Features["avx512vpopcntdq"] =
481  Features["avx512bitalg"] = Features["avx512vnni"] =
482  Features["avx512vbmi2"] = false;
483  break;
484  }
485 }
486 
487 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
488  MMX3DNowEnum Level, bool Enabled) {
489  if (Enabled) {
490  switch (Level) {
491  case AMD3DNowAthlon:
492  Features["3dnowa"] = true;
493  LLVM_FALLTHROUGH;
494  case AMD3DNow:
495  Features["3dnow"] = true;
496  LLVM_FALLTHROUGH;
497  case MMX:
498  Features["mmx"] = true;
499  LLVM_FALLTHROUGH;
500  case NoMMX3DNow:
501  break;
502  }
503  return;
504  }
505 
506  switch (Level) {
507  case NoMMX3DNow:
508  case MMX:
509  Features["mmx"] = false;
510  LLVM_FALLTHROUGH;
511  case AMD3DNow:
512  Features["3dnow"] = false;
513  LLVM_FALLTHROUGH;
514  case AMD3DNowAthlon:
515  Features["3dnowa"] = false;
516  break;
517  }
518 }
519 
520 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
521  bool Enabled) {
522  if (Enabled) {
523  switch (Level) {
524  case XOP:
525  Features["xop"] = true;
526  LLVM_FALLTHROUGH;
527  case FMA4:
528  Features["fma4"] = true;
529  setSSELevel(Features, AVX, true);
530  LLVM_FALLTHROUGH;
531  case SSE4A:
532  Features["sse4a"] = true;
533  setSSELevel(Features, SSE3, true);
534  LLVM_FALLTHROUGH;
535  case NoXOP:
536  break;
537  }
538  return;
539  }
540 
541  switch (Level) {
542  case NoXOP:
543  case SSE4A:
544  Features["sse4a"] = false;
545  LLVM_FALLTHROUGH;
546  case FMA4:
547  Features["fma4"] = false;
548  LLVM_FALLTHROUGH;
549  case XOP:
550  Features["xop"] = false;
551  break;
552  }
553 }
554 
555 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
556  StringRef Name, bool Enabled) {
557  // This is a bit of a hack to deal with the sse4 target feature when used
558  // as part of the target attribute. We handle sse4 correctly everywhere
559  // else. See below for more information on how we handle the sse4 options.
560  if (Name != "sse4")
561  Features[Name] = Enabled;
562 
563  if (Name == "mmx") {
564  setMMXLevel(Features, MMX, Enabled);
565  } else if (Name == "sse") {
566  setSSELevel(Features, SSE1, Enabled);
567  } else if (Name == "sse2") {
568  setSSELevel(Features, SSE2, Enabled);
569  } else if (Name == "sse3") {
570  setSSELevel(Features, SSE3, Enabled);
571  } else if (Name == "ssse3") {
572  setSSELevel(Features, SSSE3, Enabled);
573  } else if (Name == "sse4.2") {
574  setSSELevel(Features, SSE42, Enabled);
575  } else if (Name == "sse4.1") {
576  setSSELevel(Features, SSE41, Enabled);
577  } else if (Name == "3dnow") {
578  setMMXLevel(Features, AMD3DNow, Enabled);
579  } else if (Name == "3dnowa") {
580  setMMXLevel(Features, AMD3DNowAthlon, Enabled);
581  } else if (Name == "aes") {
582  if (Enabled)
583  setSSELevel(Features, SSE2, Enabled);
584  else
585  Features["vaes"] = false;
586  } else if (Name == "vaes") {
587  if (Enabled) {
588  setSSELevel(Features, AVX, Enabled);
589  Features["aes"] = true;
590  }
591  } else if (Name == "pclmul") {
592  if (Enabled)
593  setSSELevel(Features, SSE2, Enabled);
594  else
595  Features["vpclmulqdq"] = false;
596  } else if (Name == "vpclmulqdq") {
597  if (Enabled) {
598  setSSELevel(Features, AVX, Enabled);
599  Features["pclmul"] = true;
600  }
601  } else if (Name == "gfni") {
602  if (Enabled)
603  setSSELevel(Features, SSE2, Enabled);
604  } else if (Name == "avx") {
605  setSSELevel(Features, AVX, Enabled);
606  } else if (Name == "avx2") {
607  setSSELevel(Features, AVX2, Enabled);
608  } else if (Name == "avx512f") {
609  setSSELevel(Features, AVX512F, Enabled);
610  } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
611  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
612  Name == "avx512vbmi" || Name == "avx512ifma" ||
613  Name == "avx512vpopcntdq" || Name == "avx512bitalg" ||
614  Name == "avx512vnni" || Name == "avx512vbmi2") {
615  if (Enabled)
616  setSSELevel(Features, AVX512F, Enabled);
617  // Enable BWI instruction if VBMI/VBMI2/BITALG is being enabled.
618  if ((Name.startswith("avx512vbmi") || Name == "avx512bitalg") && Enabled)
619  Features["avx512bw"] = true;
620  // Also disable VBMI/VBMI2/BITALG if BWI is being disabled.
621  if (Name == "avx512bw" && !Enabled)
622  Features["avx512vbmi"] = Features["avx512vbmi2"] =
623  Features["avx512bitalg"] = false;
624  } else if (Name == "fma") {
625  if (Enabled)
626  setSSELevel(Features, AVX, Enabled);
627  else
628  setSSELevel(Features, AVX512F, Enabled);
629  } else if (Name == "fma4") {
630  setXOPLevel(Features, FMA4, Enabled);
631  } else if (Name == "xop") {
632  setXOPLevel(Features, XOP, Enabled);
633  } else if (Name == "sse4a") {
634  setXOPLevel(Features, SSE4A, Enabled);
635  } else if (Name == "f16c") {
636  if (Enabled)
637  setSSELevel(Features, AVX, Enabled);
638  else
639  setSSELevel(Features, AVX512F, Enabled);
640  } else if (Name == "sha") {
641  if (Enabled)
642  setSSELevel(Features, SSE2, Enabled);
643  } else if (Name == "sse4") {
644  // We can get here via the __target__ attribute since that's not controlled
645  // via the -msse4/-mno-sse4 command line alias. Handle this the same way
646  // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
647  // disabled.
648  if (Enabled)
649  setSSELevel(Features, SSE42, Enabled);
650  else
651  setSSELevel(Features, SSE41, Enabled);
652  } else if (Name == "xsave") {
653  if (!Enabled)
654  Features["xsaveopt"] = false;
655  } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
656  if (Enabled)
657  Features["xsave"] = true;
658  }
659 }
660 
661 /// handleTargetFeatures - Perform initialization based on the user
662 /// configured set of features.
663 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
664  DiagnosticsEngine &Diags) {
665  for (const auto &Feature : Features) {
666  if (Feature[0] != '+')
667  continue;
668 
669  if (Feature == "+aes") {
670  HasAES = true;
671  } else if (Feature == "+vaes") {
672  HasVAES = true;
673  } else if (Feature == "+pclmul") {
674  HasPCLMUL = true;
675  } else if (Feature == "+vpclmulqdq") {
676  HasVPCLMULQDQ = true;
677  } else if (Feature == "+lzcnt") {
678  HasLZCNT = true;
679  } else if (Feature == "+rdrnd") {
680  HasRDRND = true;
681  } else if (Feature == "+fsgsbase") {
682  HasFSGSBASE = true;
683  } else if (Feature == "+bmi") {
684  HasBMI = true;
685  } else if (Feature == "+bmi2") {
686  HasBMI2 = true;
687  } else if (Feature == "+popcnt") {
688  HasPOPCNT = true;
689  } else if (Feature == "+rtm") {
690  HasRTM = true;
691  } else if (Feature == "+prfchw") {
692  HasPRFCHW = true;
693  } else if (Feature == "+rdseed") {
694  HasRDSEED = true;
695  } else if (Feature == "+adx") {
696  HasADX = true;
697  } else if (Feature == "+tbm") {
698  HasTBM = true;
699  } else if (Feature == "+lwp") {
700  HasLWP = true;
701  } else if (Feature == "+fma") {
702  HasFMA = true;
703  } else if (Feature == "+f16c") {
704  HasF16C = true;
705  } else if (Feature == "+gfni") {
706  HasGFNI = true;
707  } else if (Feature == "+avx512cd") {
708  HasAVX512CD = true;
709  } else if (Feature == "+avx512vpopcntdq") {
710  HasAVX512VPOPCNTDQ = true;
711  } else if (Feature == "+avx512vnni") {
712  HasAVX512VNNI = true;
713  } else if (Feature == "+avx512er") {
714  HasAVX512ER = true;
715  } else if (Feature == "+avx512pf") {
716  HasAVX512PF = true;
717  } else if (Feature == "+avx512dq") {
718  HasAVX512DQ = true;
719  } else if (Feature == "+avx512bitalg") {
720  HasAVX512BITALG = true;
721  } else if (Feature == "+avx512bw") {
722  HasAVX512BW = true;
723  } else if (Feature == "+avx512vl") {
724  HasAVX512VL = true;
725  } else if (Feature == "+avx512vbmi") {
726  HasAVX512VBMI = true;
727  } else if (Feature == "+avx512vbmi2") {
728  HasAVX512VBMI2 = true;
729  } else if (Feature == "+avx512ifma") {
730  HasAVX512IFMA = true;
731  } else if (Feature == "+sha") {
732  HasSHA = true;
733  } else if (Feature == "+mpx") {
734  HasMPX = true;
735  } else if (Feature == "+shstk") {
736  HasSHSTK = true;
737  } else if (Feature == "+ibt") {
738  HasIBT = true;
739  } else if (Feature == "+movbe") {
740  HasMOVBE = true;
741  } else if (Feature == "+sgx") {
742  HasSGX = true;
743  } else if (Feature == "+cx16") {
744  HasCX16 = true;
745  } else if (Feature == "+fxsr") {
746  HasFXSR = true;
747  } else if (Feature == "+xsave") {
748  HasXSAVE = true;
749  } else if (Feature == "+xsaveopt") {
750  HasXSAVEOPT = true;
751  } else if (Feature == "+xsavec") {
752  HasXSAVEC = true;
753  } else if (Feature == "+xsaves") {
754  HasXSAVES = true;
755  } else if (Feature == "+mwaitx") {
756  HasMWAITX = true;
757  } else if (Feature == "+pku") {
758  HasPKU = true;
759  } else if (Feature == "+clflushopt") {
760  HasCLFLUSHOPT = true;
761  } else if (Feature == "+clwb") {
762  HasCLWB = true;
763  } else if (Feature == "+prefetchwt1") {
764  HasPREFETCHWT1 = true;
765  } else if (Feature == "+clzero") {
766  HasCLZERO = true;
767  } else if (Feature == "+retpoline") {
768  HasRetpoline = true;
769  } else if (Feature == "+retpoline-external-thunk") {
770  HasRetpolineExternalThunk = true;
771  }
772 
773  X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
774  .Case("+avx512f", AVX512F)
775  .Case("+avx2", AVX2)
776  .Case("+avx", AVX)
777  .Case("+sse4.2", SSE42)
778  .Case("+sse4.1", SSE41)
779  .Case("+ssse3", SSSE3)
780  .Case("+sse3", SSE3)
781  .Case("+sse2", SSE2)
782  .Case("+sse", SSE1)
783  .Default(NoSSE);
784  SSELevel = std::max(SSELevel, Level);
785 
786  MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
787  .Case("+3dnowa", AMD3DNowAthlon)
788  .Case("+3dnow", AMD3DNow)
789  .Case("+mmx", MMX)
790  .Default(NoMMX3DNow);
791  MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
792 
793  XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
794  .Case("+xop", XOP)
795  .Case("+fma4", FMA4)
796  .Case("+sse4a", SSE4A)
797  .Default(NoXOP);
798  XOPLevel = std::max(XOPLevel, XLevel);
799  }
800 
801  // LLVM doesn't have a separate switch for fpmath, so only accept it if it
802  // matches the selected sse level.
803  if ((FPMath == FP_SSE && SSELevel < SSE1) ||
804  (FPMath == FP_387 && SSELevel >= SSE1)) {
805  Diags.Report(diag::err_target_unsupported_fpmath)
806  << (FPMath == FP_SSE ? "sse" : "387");
807  return false;
808  }
809 
810  SimdDefaultAlign =
811  hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
812  return true;
813 }
814 
815 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
816 /// definitions for this particular subtarget.
818  MacroBuilder &Builder) const {
819  // Target identification.
820  if (getTriple().getArch() == llvm::Triple::x86_64) {
821  Builder.defineMacro("__amd64__");
822  Builder.defineMacro("__amd64");
823  Builder.defineMacro("__x86_64");
824  Builder.defineMacro("__x86_64__");
825  if (getTriple().getArchName() == "x86_64h") {
826  Builder.defineMacro("__x86_64h");
827  Builder.defineMacro("__x86_64h__");
828  }
829  } else {
830  DefineStd(Builder, "i386", Opts);
831  }
832 
833  // Subtarget options.
834  // FIXME: We are hard-coding the tune parameters based on the CPU, but they
835  // truly should be based on -mtune options.
836  switch (CPU) {
837  case CK_Generic:
838  break;
839  case CK_i386:
840  // The rest are coming from the i386 define above.
841  Builder.defineMacro("__tune_i386__");
842  break;
843  case CK_i486:
844  case CK_WinChipC6:
845  case CK_WinChip2:
846  case CK_C3:
847  defineCPUMacros(Builder, "i486");
848  break;
849  case CK_PentiumMMX:
850  Builder.defineMacro("__pentium_mmx__");
851  Builder.defineMacro("__tune_pentium_mmx__");
852  LLVM_FALLTHROUGH;
853  case CK_i586:
854  case CK_Pentium:
855  defineCPUMacros(Builder, "i586");
856  defineCPUMacros(Builder, "pentium");
857  break;
858  case CK_Pentium3:
859  case CK_PentiumM:
860  Builder.defineMacro("__tune_pentium3__");
861  LLVM_FALLTHROUGH;
862  case CK_Pentium2:
863  case CK_C3_2:
864  Builder.defineMacro("__tune_pentium2__");
865  LLVM_FALLTHROUGH;
866  case CK_PentiumPro:
867  defineCPUMacros(Builder, "i686");
868  defineCPUMacros(Builder, "pentiumpro");
869  break;
870  case CK_Pentium4:
871  defineCPUMacros(Builder, "pentium4");
872  break;
873  case CK_Yonah:
874  case CK_Prescott:
875  case CK_Nocona:
876  defineCPUMacros(Builder, "nocona");
877  break;
878  case CK_Core2:
879  case CK_Penryn:
880  defineCPUMacros(Builder, "core2");
881  break;
882  case CK_Bonnell:
883  defineCPUMacros(Builder, "atom");
884  break;
885  case CK_Silvermont:
886  defineCPUMacros(Builder, "slm");
887  break;
888  case CK_Goldmont:
889  defineCPUMacros(Builder, "goldmont");
890  break;
891  case CK_Nehalem:
892  case CK_Westmere:
893  case CK_SandyBridge:
894  case CK_IvyBridge:
895  case CK_Haswell:
896  case CK_Broadwell:
897  case CK_SkylakeClient:
898  case CK_SkylakeServer:
899  case CK_Cannonlake:
900  case CK_Icelake:
901  // FIXME: Historically, we defined this legacy name, it would be nice to
902  // remove it at some point. We've never exposed fine-grained names for
903  // recent primary x86 CPUs, and we should keep it that way.
904  defineCPUMacros(Builder, "corei7");
905  break;
906  case CK_KNL:
907  defineCPUMacros(Builder, "knl");
908  break;
909  case CK_KNM:
910  break;
911  case CK_Lakemont:
912  defineCPUMacros(Builder, "i586", /*Tuning*/false);
913  defineCPUMacros(Builder, "pentium", /*Tuning*/false);
914  Builder.defineMacro("__tune_lakemont__");
915  break;
916  case CK_K6_2:
917  Builder.defineMacro("__k6_2__");
918  Builder.defineMacro("__tune_k6_2__");
919  LLVM_FALLTHROUGH;
920  case CK_K6_3:
921  if (CPU != CK_K6_2) { // In case of fallthrough
922  // FIXME: GCC may be enabling these in cases where some other k6
923  // architecture is specified but -m3dnow is explicitly provided. The
924  // exact semantics need to be determined and emulated here.
925  Builder.defineMacro("__k6_3__");
926  Builder.defineMacro("__tune_k6_3__");
927  }
928  LLVM_FALLTHROUGH;
929  case CK_K6:
930  defineCPUMacros(Builder, "k6");
931  break;
932  case CK_Athlon:
933  case CK_AthlonXP:
934  defineCPUMacros(Builder, "athlon");
935  if (SSELevel != NoSSE) {
936  Builder.defineMacro("__athlon_sse__");
937  Builder.defineMacro("__tune_athlon_sse__");
938  }
939  break;
940  case CK_K8:
941  case CK_K8SSE3:
942  case CK_x86_64:
943  defineCPUMacros(Builder, "k8");
944  break;
945  case CK_AMDFAM10:
946  defineCPUMacros(Builder, "amdfam10");
947  break;
948  case CK_BTVER1:
949  defineCPUMacros(Builder, "btver1");
950  break;
951  case CK_BTVER2:
952  defineCPUMacros(Builder, "btver2");
953  break;
954  case CK_BDVER1:
955  defineCPUMacros(Builder, "bdver1");
956  break;
957  case CK_BDVER2:
958  defineCPUMacros(Builder, "bdver2");
959  break;
960  case CK_BDVER3:
961  defineCPUMacros(Builder, "bdver3");
962  break;
963  case CK_BDVER4:
964  defineCPUMacros(Builder, "bdver4");
965  break;
966  case CK_ZNVER1:
967  defineCPUMacros(Builder, "znver1");
968  break;
969  case CK_Geode:
970  defineCPUMacros(Builder, "geode");
971  break;
972  }
973 
974  // Target properties.
975  Builder.defineMacro("__REGISTER_PREFIX__", "");
976 
977  // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
978  // functions in glibc header files that use FP Stack inline asm which the
979  // backend can't deal with (PR879).
980  Builder.defineMacro("__NO_MATH_INLINES");
981 
982  if (HasAES)
983  Builder.defineMacro("__AES__");
984 
985  if (HasVAES)
986  Builder.defineMacro("__VAES__");
987 
988  if (HasPCLMUL)
989  Builder.defineMacro("__PCLMUL__");
990 
991  if (HasVPCLMULQDQ)
992  Builder.defineMacro("__VPCLMULQDQ__");
993 
994  if (HasLZCNT)
995  Builder.defineMacro("__LZCNT__");
996 
997  if (HasRDRND)
998  Builder.defineMacro("__RDRND__");
999 
1000  if (HasFSGSBASE)
1001  Builder.defineMacro("__FSGSBASE__");
1002 
1003  if (HasBMI)
1004  Builder.defineMacro("__BMI__");
1005 
1006  if (HasBMI2)
1007  Builder.defineMacro("__BMI2__");
1008 
1009  if (HasPOPCNT)
1010  Builder.defineMacro("__POPCNT__");
1011 
1012  if (HasRTM)
1013  Builder.defineMacro("__RTM__");
1014 
1015  if (HasPRFCHW)
1016  Builder.defineMacro("__PRFCHW__");
1017 
1018  if (HasRDSEED)
1019  Builder.defineMacro("__RDSEED__");
1020 
1021  if (HasADX)
1022  Builder.defineMacro("__ADX__");
1023 
1024  if (HasTBM)
1025  Builder.defineMacro("__TBM__");
1026 
1027  if (HasLWP)
1028  Builder.defineMacro("__LWP__");
1029 
1030  if (HasMWAITX)
1031  Builder.defineMacro("__MWAITX__");
1032 
1033  switch (XOPLevel) {
1034  case XOP:
1035  Builder.defineMacro("__XOP__");
1036  LLVM_FALLTHROUGH;
1037  case FMA4:
1038  Builder.defineMacro("__FMA4__");
1039  LLVM_FALLTHROUGH;
1040  case SSE4A:
1041  Builder.defineMacro("__SSE4A__");
1042  LLVM_FALLTHROUGH;
1043  case NoXOP:
1044  break;
1045  }
1046 
1047  if (HasFMA)
1048  Builder.defineMacro("__FMA__");
1049 
1050  if (HasF16C)
1051  Builder.defineMacro("__F16C__");
1052 
1053  if (HasGFNI)
1054  Builder.defineMacro("__GFNI__");
1055 
1056  if (HasAVX512CD)
1057  Builder.defineMacro("__AVX512CD__");
1058  if (HasAVX512VPOPCNTDQ)
1059  Builder.defineMacro("__AVX512VPOPCNTDQ__");
1060  if (HasAVX512VNNI)
1061  Builder.defineMacro("__AVX512VNNI__");
1062  if (HasAVX512ER)
1063  Builder.defineMacro("__AVX512ER__");
1064  if (HasAVX512PF)
1065  Builder.defineMacro("__AVX512PF__");
1066  if (HasAVX512DQ)
1067  Builder.defineMacro("__AVX512DQ__");
1068  if (HasAVX512BITALG)
1069  Builder.defineMacro("__AVX512BITALG__");
1070  if (HasAVX512BW)
1071  Builder.defineMacro("__AVX512BW__");
1072  if (HasAVX512VL)
1073  Builder.defineMacro("__AVX512VL__");
1074  if (HasAVX512VBMI)
1075  Builder.defineMacro("__AVX512VBMI__");
1076  if (HasAVX512VBMI2)
1077  Builder.defineMacro("__AVX512VBMI2__");
1078  if (HasAVX512IFMA)
1079  Builder.defineMacro("__AVX512IFMA__");
1080 
1081  if (HasSHA)
1082  Builder.defineMacro("__SHA__");
1083 
1084  if (HasFXSR)
1085  Builder.defineMacro("__FXSR__");
1086  if (HasXSAVE)
1087  Builder.defineMacro("__XSAVE__");
1088  if (HasXSAVEOPT)
1089  Builder.defineMacro("__XSAVEOPT__");
1090  if (HasXSAVEC)
1091  Builder.defineMacro("__XSAVEC__");
1092  if (HasXSAVES)
1093  Builder.defineMacro("__XSAVES__");
1094  if (HasPKU)
1095  Builder.defineMacro("__PKU__");
1096  if (HasCX16)
1097  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
1098  if (HasCLFLUSHOPT)
1099  Builder.defineMacro("__CLFLUSHOPT__");
1100  if (HasCLWB)
1101  Builder.defineMacro("__CLWB__");
1102  if (HasMPX)
1103  Builder.defineMacro("__MPX__");
1104  if (HasSHSTK)
1105  Builder.defineMacro("__SHSTK__");
1106  if (HasSGX)
1107  Builder.defineMacro("__SGX__");
1108  if (HasPREFETCHWT1)
1109  Builder.defineMacro("__PREFETCHWT1__");
1110  if (HasCLZERO)
1111  Builder.defineMacro("__CLZERO__");
1112 
1113  // Each case falls through to the previous one here.
1114  switch (SSELevel) {
1115  case AVX512F:
1116  Builder.defineMacro("__AVX512F__");
1117  LLVM_FALLTHROUGH;
1118  case AVX2:
1119  Builder.defineMacro("__AVX2__");
1120  LLVM_FALLTHROUGH;
1121  case AVX:
1122  Builder.defineMacro("__AVX__");
1123  LLVM_FALLTHROUGH;
1124  case SSE42:
1125  Builder.defineMacro("__SSE4_2__");
1126  LLVM_FALLTHROUGH;
1127  case SSE41:
1128  Builder.defineMacro("__SSE4_1__");
1129  LLVM_FALLTHROUGH;
1130  case SSSE3:
1131  Builder.defineMacro("__SSSE3__");
1132  LLVM_FALLTHROUGH;
1133  case SSE3:
1134  Builder.defineMacro("__SSE3__");
1135  LLVM_FALLTHROUGH;
1136  case SSE2:
1137  Builder.defineMacro("__SSE2__");
1138  Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
1139  LLVM_FALLTHROUGH;
1140  case SSE1:
1141  Builder.defineMacro("__SSE__");
1142  Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
1143  LLVM_FALLTHROUGH;
1144  case NoSSE:
1145  break;
1146  }
1147 
1148  if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
1149  switch (SSELevel) {
1150  case AVX512F:
1151  case AVX2:
1152  case AVX:
1153  case SSE42:
1154  case SSE41:
1155  case SSSE3:
1156  case SSE3:
1157  case SSE2:
1158  Builder.defineMacro("_M_IX86_FP", Twine(2));
1159  break;
1160  case SSE1:
1161  Builder.defineMacro("_M_IX86_FP", Twine(1));
1162  break;
1163  default:
1164  Builder.defineMacro("_M_IX86_FP", Twine(0));
1165  break;
1166  }
1167  }
1168 
1169  // Each case falls through to the previous one here.
1170  switch (MMX3DNowLevel) {
1171  case AMD3DNowAthlon:
1172  Builder.defineMacro("__3dNOW_A__");
1173  LLVM_FALLTHROUGH;
1174  case AMD3DNow:
1175  Builder.defineMacro("__3dNOW__");
1176  LLVM_FALLTHROUGH;
1177  case MMX:
1178  Builder.defineMacro("__MMX__");
1179  LLVM_FALLTHROUGH;
1180  case NoMMX3DNow:
1181  break;
1182  }
1183 
1184  if (CPU >= CK_i486) {
1185  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1186  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1187  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1188  }
1189  if (CPU >= CK_i586)
1190  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1191 
1192  if (HasFloat128)
1193  Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
1194 }
1195 
1196 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
1197  return llvm::StringSwitch<bool>(Name)
1198  .Case("3dnow", true)
1199  .Case("3dnowa", true)
1200  .Case("adx", true)
1201  .Case("aes", true)
1202  .Case("avx", true)
1203  .Case("avx2", true)
1204  .Case("avx512f", true)
1205  .Case("avx512cd", true)
1206  .Case("avx512vpopcntdq", true)
1207  .Case("avx512vnni", true)
1208  .Case("avx512er", true)
1209  .Case("avx512pf", true)
1210  .Case("avx512dq", true)
1211  .Case("avx512bitalg", true)
1212  .Case("avx512bw", true)
1213  .Case("avx512vl", true)
1214  .Case("avx512vbmi", true)
1215  .Case("avx512vbmi2", true)
1216  .Case("avx512ifma", true)
1217  .Case("bmi", true)
1218  .Case("bmi2", true)
1219  .Case("clflushopt", true)
1220  .Case("clwb", true)
1221  .Case("clzero", true)
1222  .Case("cx16", true)
1223  .Case("f16c", true)
1224  .Case("fma", true)
1225  .Case("fma4", true)
1226  .Case("fsgsbase", true)
1227  .Case("fxsr", true)
1228  .Case("gfni", true)
1229  .Case("lwp", true)
1230  .Case("lzcnt", true)
1231  .Case("mmx", true)
1232  .Case("movbe", true)
1233  .Case("mpx", true)
1234  .Case("mwaitx", true)
1235  .Case("pclmul", true)
1236  .Case("pku", true)
1237  .Case("popcnt", true)
1238  .Case("prefetchwt1", true)
1239  .Case("prfchw", true)
1240  .Case("rdrnd", true)
1241  .Case("rdseed", true)
1242  .Case("rtm", true)
1243  .Case("sgx", true)
1244  .Case("sha", true)
1245  .Case("shstk", true)
1246  .Case("sse", true)
1247  .Case("sse2", true)
1248  .Case("sse3", true)
1249  .Case("ssse3", true)
1250  .Case("sse4", true)
1251  .Case("sse4.1", true)
1252  .Case("sse4.2", true)
1253  .Case("sse4a", true)
1254  .Case("tbm", true)
1255  .Case("vaes", true)
1256  .Case("vpclmulqdq", true)
1257  .Case("x87", true)
1258  .Case("xop", true)
1259  .Case("xsave", true)
1260  .Case("xsavec", true)
1261  .Case("xsaves", true)
1262  .Case("xsaveopt", true)
1263  .Default(false);
1264 }
1265 
1266 bool X86TargetInfo::hasFeature(StringRef Feature) const {
1267  return llvm::StringSwitch<bool>(Feature)
1268  .Case("adx", HasADX)
1269  .Case("aes", HasAES)
1270  .Case("avx", SSELevel >= AVX)
1271  .Case("avx2", SSELevel >= AVX2)
1272  .Case("avx512f", SSELevel >= AVX512F)
1273  .Case("avx512cd", HasAVX512CD)
1274  .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
1275  .Case("avx512vnni", HasAVX512VNNI)
1276  .Case("avx512er", HasAVX512ER)
1277  .Case("avx512pf", HasAVX512PF)
1278  .Case("avx512dq", HasAVX512DQ)
1279  .Case("avx512bitalg", HasAVX512BITALG)
1280  .Case("avx512bw", HasAVX512BW)
1281  .Case("avx512vl", HasAVX512VL)
1282  .Case("avx512vbmi", HasAVX512VBMI)
1283  .Case("avx512vbmi2", HasAVX512VBMI2)
1284  .Case("avx512ifma", HasAVX512IFMA)
1285  .Case("bmi", HasBMI)
1286  .Case("bmi2", HasBMI2)
1287  .Case("clflushopt", HasCLFLUSHOPT)
1288  .Case("clwb", HasCLWB)
1289  .Case("clzero", HasCLZERO)
1290  .Case("cx16", HasCX16)
1291  .Case("f16c", HasF16C)
1292  .Case("fma", HasFMA)
1293  .Case("fma4", XOPLevel >= FMA4)
1294  .Case("fsgsbase", HasFSGSBASE)
1295  .Case("fxsr", HasFXSR)
1296  .Case("gfni", HasGFNI)
1297  .Case("ibt", HasIBT)
1298  .Case("lwp", HasLWP)
1299  .Case("lzcnt", HasLZCNT)
1300  .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
1301  .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
1302  .Case("mmx", MMX3DNowLevel >= MMX)
1303  .Case("movbe", HasMOVBE)
1304  .Case("mpx", HasMPX)
1305  .Case("mwaitx", HasMWAITX)
1306  .Case("pclmul", HasPCLMUL)
1307  .Case("pku", HasPKU)
1308  .Case("popcnt", HasPOPCNT)
1309  .Case("prefetchwt1", HasPREFETCHWT1)
1310  .Case("prfchw", HasPRFCHW)
1311  .Case("rdrnd", HasRDRND)
1312  .Case("rdseed", HasRDSEED)
1313  .Case("retpoline", HasRetpoline)
1314  .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
1315  .Case("rtm", HasRTM)
1316  .Case("sgx", HasSGX)
1317  .Case("sha", HasSHA)
1318  .Case("shstk", HasSHSTK)
1319  .Case("sse", SSELevel >= SSE1)
1320  .Case("sse2", SSELevel >= SSE2)
1321  .Case("sse3", SSELevel >= SSE3)
1322  .Case("ssse3", SSELevel >= SSSE3)
1323  .Case("sse4.1", SSELevel >= SSE41)
1324  .Case("sse4.2", SSELevel >= SSE42)
1325  .Case("sse4a", XOPLevel >= SSE4A)
1326  .Case("tbm", HasTBM)
1327  .Case("vaes", HasVAES)
1328  .Case("vpclmulqdq", HasVPCLMULQDQ)
1329  .Case("x86", true)
1330  .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1331  .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1332  .Case("xop", XOPLevel >= XOP)
1333  .Case("xsave", HasXSAVE)
1334  .Case("xsavec", HasXSAVEC)
1335  .Case("xsaves", HasXSAVES)
1336  .Case("xsaveopt", HasXSAVEOPT)
1337  .Default(false);
1338 }
1339 
1340 // We can't use a generic validation scheme for the features accepted here
1341 // versus subtarget features accepted in the target attribute because the
1342 // bitfield structure that's initialized in the runtime only supports the
1343 // below currently rather than the full range of subtarget features. (See
1344 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
1345 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1346  return llvm::StringSwitch<bool>(FeatureStr)
1347 #define X86_FEATURE_COMPAT(VAL, ENUM, STR) .Case(STR, true)
1348 #include "llvm/Support/X86TargetParser.def"
1349  .Default(false);
1350 }
1351 
1352 // We can't use a generic validation scheme for the cpus accepted here
1353 // versus subtarget cpus accepted in the target attribute because the
1354 // variables intitialized by the runtime only support the below currently
1355 // rather than the full range of cpus.
1356 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1357  return llvm::StringSwitch<bool>(FeatureStr)
1358 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1359 #define X86_CPU_TYPE_COMPAT_WITH_ALIAS(ARCHNAME, ENUM, STR, ALIAS) \
1360  .Cases(STR, ALIAS, true)
1361 #define X86_CPU_TYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1362 #define X86_CPU_SUBTYPE_COMPAT(ARCHNAME, ENUM, STR) .Case(STR, true)
1363 #include "llvm/Support/X86TargetParser.def"
1364  .Default(false);
1365 }
1366 
1368  const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1369  switch (*Name) {
1370  default:
1371  return false;
1372  // Constant constraints.
1373  case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1374  // instructions.
1375  case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1376  // x86_64 instructions.
1377  case 's':
1378  Info.setRequiresImmediate();
1379  return true;
1380  case 'I':
1381  Info.setRequiresImmediate(0, 31);
1382  return true;
1383  case 'J':
1384  Info.setRequiresImmediate(0, 63);
1385  return true;
1386  case 'K':
1387  Info.setRequiresImmediate(-128, 127);
1388  return true;
1389  case 'L':
1390  Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1391  return true;
1392  case 'M':
1393  Info.setRequiresImmediate(0, 3);
1394  return true;
1395  case 'N':
1396  Info.setRequiresImmediate(0, 255);
1397  return true;
1398  case 'O':
1399  Info.setRequiresImmediate(0, 127);
1400  return true;
1401  // Register constraints.
1402  case 'Y': // 'Y' is the first character for several 2-character constraints.
1403  // Shift the pointer to the second character of the constraint.
1404  Name++;
1405  switch (*Name) {
1406  default:
1407  return false;
1408  case 'z':
1409  case '0': // First SSE register.
1410  case '2':
1411  case 't': // Any SSE register, when SSE2 is enabled.
1412  case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1413  case 'm': // Any MMX register, when inter-unit moves enabled.
1414  case 'k': // AVX512 arch mask registers: k1-k7.
1415  Info.setAllowsRegister();
1416  return true;
1417  }
1418  case 'f': // Any x87 floating point stack register.
1419  // Constraint 'f' cannot be used for output operands.
1420  if (Info.ConstraintStr[0] == '=')
1421  return false;
1422  Info.setAllowsRegister();
1423  return true;
1424  case 'a': // eax.
1425  case 'b': // ebx.
1426  case 'c': // ecx.
1427  case 'd': // edx.
1428  case 'S': // esi.
1429  case 'D': // edi.
1430  case 'A': // edx:eax.
1431  case 't': // Top of floating point stack.
1432  case 'u': // Second from top of floating point stack.
1433  case 'q': // Any register accessible as [r]l: a, b, c, and d.
1434  case 'y': // Any MMX register.
1435  case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1436  case 'x': // Any SSE register.
1437  case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
1438  // for intermideate k reg operations).
1439  case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1440  case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1441  case 'l': // "Index" registers: any general register that can be used as an
1442  // index in a base+index memory access.
1443  Info.setAllowsRegister();
1444  return true;
1445  // Floating point constant constraints.
1446  case 'C': // SSE floating point constant.
1447  case 'G': // x87 floating point constant.
1448  return true;
1449  }
1450 }
1451 
1452 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
1453  unsigned Size) const {
1454  // Strip off constraint modifiers.
1455  while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1456  Constraint = Constraint.substr(1);
1457 
1458  return validateOperandSize(Constraint, Size);
1459 }
1460 
1461 bool X86TargetInfo::validateInputSize(StringRef Constraint,
1462  unsigned Size) const {
1463  return validateOperandSize(Constraint, Size);
1464 }
1465 
1466 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
1467  unsigned Size) const {
1468  switch (Constraint[0]) {
1469  default:
1470  break;
1471  case 'k':
1472  // Registers k0-k7 (AVX512) size limit is 64 bit.
1473  case 'y':
1474  return Size <= 64;
1475  case 'f':
1476  case 't':
1477  case 'u':
1478  return Size <= 128;
1479  case 'Y':
1480  // 'Y' is the first character for several 2-character constraints.
1481  switch (Constraint[1]) {
1482  default:
1483  return false;
1484  case 'm':
1485  // 'Ym' is synonymous with 'y'.
1486  case 'k':
1487  return Size <= 64;
1488  case 'z':
1489  case '0':
1490  // XMM0
1491  if (SSELevel >= SSE1)
1492  return Size <= 128U;
1493  return false;
1494  case 'i':
1495  case 't':
1496  case '2':
1497  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1498  if (SSELevel < SSE2)
1499  return false;
1500  break;
1501  }
1502  case 'v':
1503  case 'x':
1504  if (SSELevel >= AVX512F)
1505  // 512-bit zmm registers can be used if target supports AVX512F.
1506  return Size <= 512U;
1507  else if (SSELevel >= AVX)
1508  // 256-bit ymm registers can be used if target supports AVX.
1509  return Size <= 256U;
1510  return Size <= 128U;
1511 
1512  }
1513 
1514  return true;
1515 }
1516 
1517 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1518  switch (*Constraint) {
1519  case 'a':
1520  return std::string("{ax}");
1521  case 'b':
1522  return std::string("{bx}");
1523  case 'c':
1524  return std::string("{cx}");
1525  case 'd':
1526  return std::string("{dx}");
1527  case 'S':
1528  return std::string("{si}");
1529  case 'D':
1530  return std::string("{di}");
1531  case 'p': // address
1532  return std::string("im");
1533  case 't': // top of floating point stack.
1534  return std::string("{st}");
1535  case 'u': // second from top of floating point stack.
1536  return std::string("{st(1)}"); // second from top of floating point stack.
1537  case 'Y':
1538  switch (Constraint[1]) {
1539  default:
1540  // Break from inner switch and fall through (copy single char),
1541  // continue parsing after copying the current constraint into
1542  // the return string.
1543  break;
1544  case 'k':
1545  case 'm':
1546  case 'i':
1547  case 't':
1548  case 'z':
1549  case '0':
1550  case '2':
1551  // "^" hints llvm that this is a 2 letter constraint.
1552  // "Constraint++" is used to promote the string iterator
1553  // to the next constraint.
1554  return std::string("^") + std::string(Constraint++, 2);
1555  }
1556  LLVM_FALLTHROUGH;
1557  default:
1558  return std::string(1, *Constraint);
1559  }
1560 }
1561 
1562 bool X86TargetInfo::checkCPUKind(CPUKind Kind) const {
1563  // Perform any per-CPU checks necessary to determine if this CPU is
1564  // acceptable.
1565  // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1566  // invalid without explaining *why*.
1567  switch (Kind) {
1568  case CK_Generic:
1569  // No processor selected!
1570  return false;
1571 #define PROC(ENUM, STRING, IS64BIT) \
1572  case CK_##ENUM: \
1573  return IS64BIT || getTriple().getArch() == llvm::Triple::x86;
1574 #include "clang/Basic/X86Target.def"
1575  }
1576  llvm_unreachable("Unhandled CPU kind");
1577 }
1578 
1579 X86TargetInfo::CPUKind X86TargetInfo::getCPUKind(StringRef CPU) const {
1580  return llvm::StringSwitch<CPUKind>(CPU)
1581 #define PROC(ENUM, STRING, IS64BIT) .Case(STRING, CK_##ENUM)
1582 #define PROC_ALIAS(ENUM, ALIAS) .Case(ALIAS, CK_##ENUM)
1583 #include "clang/Basic/X86Target.def"
1584  .Default(CK_Generic);
1585 }
1586 
1588  return llvm::makeArrayRef(GCCRegNames);
1589 }
1590 
1592  return llvm::makeArrayRef(AddlRegNames);
1593 }
1594 
1596  return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1598 }
1599 
1601  return llvm::makeArrayRef(BuiltinInfoX86,
1603 }
void DefineStd(MacroBuilder &Builder, StringRef MacroName, const LangOptions &Opts)
DefineStd - Define a macro name and standard variants.
Definition: Targets.cpp:53
static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, const TargetInfo &Target)
Determine whether a translation unit built using the current language options has the given feature...
Definition: Module.cpp:73
bool setFPMath(StringRef Name) override
Use the specified unit for FP math.
Definition: X86.cpp:91
const Builtin::Info BuiltinInfoX86[]
Definition: X86.cpp:24
static void setMMXLevel(llvm::StringMap< bool > &Features, MMX3DNowEnum Level, bool Enabled)
Definition: X86.cpp:487
DiagnosticBuilder Report(SourceLocation Loc, unsigned DiagID)
Issue the message to the client.
Definition: Diagnostic.h:1207
bool validateOutputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1452
ArrayRef< TargetInfo::AddlRegName > getGCCAddlRegNames() const override
Definition: X86.cpp:1591
void setRequiresImmediate(int Min, int Max)
Definition: TargetInfo.h:694
virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const
Definition: X86.cpp:1466
static void setXOPLevel(llvm::StringMap< bool > &Features, XOPEnum Level, bool Enabled)
Definition: X86.cpp:520
const TargetInfo::AddlRegName AddlRegNames[]
Definition: X86.cpp:66
Keeps track of the various options that can be enabled, which controls the dialect of C or C++ that i...
Definition: LangOptions.h:48
bool validateCpuSupports(StringRef Name) const override
Definition: X86.cpp:1345
#define X86_FEATURE_COMPAT(VAL, ENUM, STR)
Concrete class used by the front-end to report problems and issues.
Definition: Diagnostic.h:147
Defines the Diagnostic-related interfaces.
bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override
Definition: X86.cpp:1367
static const char *const GCCRegNames[]
Definition: X86.cpp:42
bool isValidFeatureName(StringRef Name) const override
Determine whether this TargetInfo supports the given feature.
Definition: X86.cpp:1196
#define X86_VENDOR(ENUM, STRING)
virtual bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeatureVec) const
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: TargetInfo.cpp:347
bool hasFeature(StringRef Feature) const override
Determine whether the given target has the given feature.
Definition: X86.cpp:1266
static void setSSELevel(llvm::StringMap< bool > &Features, X86SSEEnum Level, bool Enabled)
Definition: X86.cpp:408
Enumerates target-specific builtins in their own namespaces within namespace clang.
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1600
Kind
std::string convertConstraint(const char *&Constraint) const override
Definition: X86.cpp:1517
ArrayRef< Builtin::Info > getTargetBuiltins() const override
Return information about target-specific builtins for the current primary target, and info about whic...
Definition: X86.cpp:1595
Dataflow Directional Tag Classes.
bool handleTargetFeatures(std::vector< std::string > &Features, DiagnosticsEngine &Diags) override
handleTargetFeatures - Perform initialization based on the user configured set of features...
Definition: X86.cpp:663
bool validateInputSize(StringRef Constraint, unsigned Size) const override
Definition: X86.cpp:1461
void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override
X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro definitions for this parti...
Definition: X86.cpp:817
#define PROC(ENUM, STRING, IS64BIT)
char __ovld __cnfn max(char x, char y)
Returns y if x < y, otherwise it returns x.
void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, bool Tuning)
Definition: Targets.cpp:69
void defineMacro(const Twine &Name, const Twine &Value="1")
Append a #define line for macro of the form "\#define Name Value\n".
Definition: MacroBuilder.h:30
static void setFeatureEnabledImpl(llvm::StringMap< bool > &Features, StringRef Name, bool Enabled)
Definition: X86.cpp:555
bool validateCpuIs(StringRef Name) const override
Definition: X86.cpp:1356
ArrayRef< const char * > getGCCRegNames() const override
Definition: X86.cpp:1587
Defines enum values for all the target-independent builtin functions.
bool initFeatureMap(llvm::StringMap< bool > &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector< std::string > &FeaturesVec) const override
Initialize the map with the default set of target features for the CPU this should include all legal ...
Definition: X86.cpp:103