clang  8.0.0
TargetInfo.cpp
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1 //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // These classes wrap the information about a call or function
11 // definition used to handle ABI compliancy.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "TargetInfo.h"
16 #include "ABIInfo.h"
17 #include "CGBlocks.h"
18 #include "CGCXXABI.h"
19 #include "CGValue.h"
20 #include "CodeGenFunction.h"
21 #include "clang/AST/RecordLayout.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include <algorithm> // std::sort
33 
34 using namespace clang;
35 using namespace CodeGen;
36 
37 // Helper for coercing an aggregate argument or return value into an integer
38 // array of the same size (including padding) and alignment. This alternate
39 // coercion happens only for the RenderScript ABI and can be removed after
40 // runtimes that rely on it are no longer supported.
41 //
42 // RenderScript assumes that the size of the argument / return value in the IR
43 // is the same as the size of the corresponding qualified type. This helper
44 // coerces the aggregate type into an array of the same size (including
45 // padding). This coercion is used in lieu of expansion of struct members or
46 // other canonical coercions that return a coerced-type of larger size.
47 //
48 // Ty - The argument / return value type
49 // Context - The associated ASTContext
50 // LLVMContext - The associated LLVMContext
52  ASTContext &Context,
53  llvm::LLVMContext &LLVMContext) {
54  // Alignment and Size are measured in bits.
55  const uint64_t Size = Context.getTypeSize(Ty);
56  const uint64_t Alignment = Context.getTypeAlign(Ty);
57  llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
58  const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
59  return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
60 }
61 
63  llvm::Value *Array,
65  unsigned FirstIndex,
66  unsigned LastIndex) {
67  // Alternatively, we could emit this as a loop in the source.
68  for (unsigned I = FirstIndex; I <= LastIndex; ++I) {
69  llvm::Value *Cell =
70  Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I);
71  Builder.CreateAlignedStore(Value, Cell, CharUnits::One());
72  }
73 }
74 
78 }
79 
81 ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByRef, bool Realign,
82  llvm::Type *Padding) const {
83  return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty),
84  ByRef, Realign, Padding);
85 }
86 
89  return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty),
90  /*ByRef*/ false, Realign);
91 }
92 
94  QualType Ty) const {
95  return Address::invalid();
96 }
97 
99 
100 /// Does the given lowering require more than the given number of
101 /// registers when expanded?
102 ///
103 /// This is intended to be the basis of a reasonable basic implementation
104 /// of should{Pass,Return}IndirectlyForSwift.
105 ///
106 /// For most targets, a limit of four total registers is reasonable; this
107 /// limits the amount of code required in order to move around the value
108 /// in case it wasn't produced immediately prior to the call by the caller
109 /// (or wasn't produced in exactly the right registers) or isn't used
110 /// immediately within the callee. But some targets may need to further
111 /// limit the register count due to an inability to support that many
112 /// return registers.
114  ArrayRef<llvm::Type*> scalarTypes,
115  unsigned maxAllRegisters) {
116  unsigned intCount = 0, fpCount = 0;
117  for (llvm::Type *type : scalarTypes) {
118  if (type->isPointerTy()) {
119  intCount++;
120  } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) {
121  auto ptrWidth = cgt.getTarget().getPointerWidth(0);
122  intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth;
123  } else {
124  assert(type->isVectorTy() || type->isFloatingPointTy());
125  fpCount++;
126  }
127  }
128 
129  return (intCount + fpCount > maxAllRegisters);
130 }
131 
133  llvm::Type *eltTy,
134  unsigned numElts) const {
135  // The default implementation of this assumes that the target guarantees
136  // 128-bit SIMD support but nothing more.
137  return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16);
138 }
139 
141  CGCXXABI &CXXABI) {
142  const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl());
143  if (!RD) {
144  if (!RT->getDecl()->canPassInRegisters())
145  return CGCXXABI::RAA_Indirect;
146  return CGCXXABI::RAA_Default;
147  }
148  return CXXABI.getRecordArgABI(RD);
149 }
150 
152  CGCXXABI &CXXABI) {
153  const RecordType *RT = T->getAs<RecordType>();
154  if (!RT)
155  return CGCXXABI::RAA_Default;
156  return getRecordArgABI(RT, CXXABI);
157 }
158 
160  const ABIInfo &Info) {
161  QualType Ty = FI.getReturnType();
162 
163  if (const auto *RT = Ty->getAs<RecordType>())
164  if (!isa<CXXRecordDecl>(RT->getDecl()) &&
165  !RT->getDecl()->canPassInRegisters()) {
166  FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty);
167  return true;
168  }
169 
170  return CXXABI.classifyReturnType(FI);
171 }
172 
173 /// Pass transparent unions as if they were the type of the first element. Sema
174 /// should ensure that all elements of the union have the same "machine type".
176  if (const RecordType *UT = Ty->getAsUnionType()) {
177  const RecordDecl *UD = UT->getDecl();
178  if (UD->hasAttr<TransparentUnionAttr>()) {
179  assert(!UD->field_empty() && "sema created an empty transparent union");
180  return UD->field_begin()->getType();
181  }
182  }
183  return Ty;
184 }
185 
187  return CGT.getCXXABI();
188 }
189 
191  return CGT.getContext();
192 }
193 
194 llvm::LLVMContext &ABIInfo::getVMContext() const {
195  return CGT.getLLVMContext();
196 }
197 
198 const llvm::DataLayout &ABIInfo::getDataLayout() const {
199  return CGT.getDataLayout();
200 }
201 
203  return CGT.getTarget();
204 }
205 
207  return CGT.getCodeGenOpts();
208 }
209 
210 bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); }
211 
213  return false;
214 }
215 
217  uint64_t Members) const {
218  return false;
219 }
220 
221 LLVM_DUMP_METHOD void ABIArgInfo::dump() const {
222  raw_ostream &OS = llvm::errs();
223  OS << "(ABIArgInfo Kind=";
224  switch (TheKind) {
225  case Direct:
226  OS << "Direct Type=";
227  if (llvm::Type *Ty = getCoerceToType())
228  Ty->print(OS);
229  else
230  OS << "null";
231  break;
232  case Extend:
233  OS << "Extend";
234  break;
235  case Ignore:
236  OS << "Ignore";
237  break;
238  case InAlloca:
239  OS << "InAlloca Offset=" << getInAllocaFieldIndex();
240  break;
241  case Indirect:
242  OS << "Indirect Align=" << getIndirectAlign().getQuantity()
243  << " ByVal=" << getIndirectByVal()
244  << " Realign=" << getIndirectRealign();
245  break;
246  case Expand:
247  OS << "Expand";
248  break;
249  case CoerceAndExpand:
250  OS << "CoerceAndExpand Type=";
251  getCoerceAndExpandType()->print(OS);
252  break;
253  }
254  OS << ")\n";
255 }
256 
257 // Dynamically round a pointer up to a multiple of the given alignment.
259  llvm::Value *Ptr,
260  CharUnits Align) {
261  llvm::Value *PtrAsInt = Ptr;
262  // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align;
263  PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy);
264  PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt,
265  llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1));
266  PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt,
267  llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity()));
268  PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt,
269  Ptr->getType(),
270  Ptr->getName() + ".aligned");
271  return PtrAsInt;
272 }
273 
274 /// Emit va_arg for a platform using the common void* representation,
275 /// where arguments are simply emitted in an array of slots on the stack.
276 ///
277 /// This version implements the core direct-value passing rules.
278 ///
279 /// \param SlotSize - The size and alignment of a stack slot.
280 /// Each argument will be allocated to a multiple of this number of
281 /// slots, and all the slots will be aligned to this value.
282 /// \param AllowHigherAlign - The slot alignment is not a cap;
283 /// an argument type with an alignment greater than the slot size
284 /// will be emitted on a higher-alignment address, potentially
285 /// leaving one or more empty slots behind as padding. If this
286 /// is false, the returned address might be less-aligned than
287 /// DirectAlign.
289  Address VAListAddr,
290  llvm::Type *DirectTy,
291  CharUnits DirectSize,
292  CharUnits DirectAlign,
293  CharUnits SlotSize,
294  bool AllowHigherAlign) {
295  // Cast the element type to i8* if necessary. Some platforms define
296  // va_list as a struct containing an i8* instead of just an i8*.
297  if (VAListAddr.getElementType() != CGF.Int8PtrTy)
298  VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy);
299 
300  llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur");
301 
302  // If the CC aligns values higher than the slot size, do so if needed.
303  Address Addr = Address::invalid();
304  if (AllowHigherAlign && DirectAlign > SlotSize) {
305  Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign),
306  DirectAlign);
307  } else {
308  Addr = Address(Ptr, SlotSize);
309  }
310 
311  // Advance the pointer past the argument, then store that back.
312  CharUnits FullDirectSize = DirectSize.alignTo(SlotSize);
313  llvm::Value *NextPtr =
314  CGF.Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), FullDirectSize,
315  "argp.next");
316  CGF.Builder.CreateStore(NextPtr, VAListAddr);
317 
318  // If the argument is smaller than a slot, and this is a big-endian
319  // target, the argument will be right-adjusted in its slot.
320  if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
321  !DirectTy->isStructTy()) {
322  Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
323  }
324 
325  Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy);
326  return Addr;
327 }
328 
329 /// Emit va_arg for a platform using the common void* representation,
330 /// where arguments are simply emitted in an array of slots on the stack.
331 ///
332 /// \param IsIndirect - Values of this type are passed indirectly.
333 /// \param ValueInfo - The size and alignment of this type, generally
334 /// computed with getContext().getTypeInfoInChars(ValueTy).
335 /// \param SlotSizeAndAlign - The size and alignment of a stack slot.
336 /// Each argument will be allocated to a multiple of this number of
337 /// slots, and all the slots will be aligned to this value.
338 /// \param AllowHigherAlign - The slot alignment is not a cap;
339 /// an argument type with an alignment greater than the slot size
340 /// will be emitted on a higher-alignment address, potentially
341 /// leaving one or more empty slots behind as padding.
343  QualType ValueTy, bool IsIndirect,
344  std::pair<CharUnits, CharUnits> ValueInfo,
345  CharUnits SlotSizeAndAlign,
346  bool AllowHigherAlign) {
347  // The size and alignment of the value that was passed directly.
348  CharUnits DirectSize, DirectAlign;
349  if (IsIndirect) {
350  DirectSize = CGF.getPointerSize();
351  DirectAlign = CGF.getPointerAlign();
352  } else {
353  DirectSize = ValueInfo.first;
354  DirectAlign = ValueInfo.second;
355  }
356 
357  // Cast the address we've calculated to the right type.
358  llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy);
359  if (IsIndirect)
360  DirectTy = DirectTy->getPointerTo(0);
361 
362  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy,
363  DirectSize, DirectAlign,
364  SlotSizeAndAlign,
365  AllowHigherAlign);
366 
367  if (IsIndirect) {
368  Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.second);
369  }
370 
371  return Addr;
372 
373 }
374 
376  Address Addr1, llvm::BasicBlock *Block1,
377  Address Addr2, llvm::BasicBlock *Block2,
378  const llvm::Twine &Name = "") {
379  assert(Addr1.getType() == Addr2.getType());
380  llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name);
381  PHI->addIncoming(Addr1.getPointer(), Block1);
382  PHI->addIncoming(Addr2.getPointer(), Block2);
383  CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment());
384  return Address(PHI, Align);
385 }
386 
388 
389 // If someone can figure out a general rule for this, that would be great.
390 // It's probably just doomed to be platform-dependent, though.
392  // Verified for:
393  // x86-64 FreeBSD, Linux, Darwin
394  // x86-32 FreeBSD, Linux, Darwin
395  // PowerPC Linux, Darwin
396  // ARM Darwin (*not* EABI)
397  // AArch64 Linux
398  return 32;
399 }
400 
402  const FunctionNoProtoType *fnType) const {
403  // The following conventions are known to require this to be false:
404  // x86_stdcall
405  // MIPS
406  // For everything else, we just prefer false unless we opt out.
407  return false;
408 }
409 
410 void
412  llvm::SmallString<24> &Opt) const {
413  // This assumes the user is passing a library name like "rt" instead of a
414  // filename like "librt.a/so", and that they don't care whether it's static or
415  // dynamic.
416  Opt = "-l";
417  Opt += Lib;
418 }
419 
421  // OpenCL kernels are called via an explicit runtime API with arguments
422  // set with clSetKernelArg(), not as normal sub-functions.
423  // Return SPIR_KERNEL by default as the kernel calling convention to
424  // ensure the fingerprint is fixed such way that each OpenCL argument
425  // gets one matching argument in the produced kernel function argument
426  // list to enable feasible implementation of clSetKernelArg() with
427  // aggregates etc. In case we would use the default C calling conv here,
428  // clSetKernelArg() might break depending on the target-specific
429  // conventions; different targets might split structs passed as values
430  // to multiple function arguments etc.
431  return llvm::CallingConv::SPIR_KERNEL;
432 }
433 
435  llvm::PointerType *T, QualType QT) const {
436  return llvm::ConstantPointerNull::get(T);
437 }
438 
440  const VarDecl *D) const {
441  assert(!CGM.getLangOpts().OpenCL &&
442  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
443  "Address space agnostic languages only");
444  return D ? D->getType().getAddressSpace() : LangAS::Default;
445 }
446 
448  CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr,
449  LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const {
450  // Since target may map different address spaces in AST to the same address
451  // space, an address space conversion may end up as a bitcast.
452  if (auto *C = dyn_cast<llvm::Constant>(Src))
453  return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy);
454  return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast(Src, DestTy);
455 }
456 
457 llvm::Constant *
459  LangAS SrcAddr, LangAS DestAddr,
460  llvm::Type *DestTy) const {
461  // Since target may map different address spaces in AST to the same address
462  // space, an address space conversion may end up as a bitcast.
463  return llvm::ConstantExpr::getPointerCast(Src, DestTy);
464 }
465 
467 TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const {
468  return C.getOrInsertSyncScopeID(""); /* default sync scope */
469 }
470 
471 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays);
472 
473 /// isEmptyField - Return true iff a the field is "empty", that is it
474 /// is an unnamed bit-field or an (array of) empty record(s).
475 static bool isEmptyField(ASTContext &Context, const FieldDecl *FD,
476  bool AllowArrays) {
477  if (FD->isUnnamedBitfield())
478  return true;
479 
480  QualType FT = FD->getType();
481 
482  // Constant arrays of empty records count as empty, strip them off.
483  // Constant arrays of zero length always count as empty.
484  if (AllowArrays)
485  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
486  if (AT->getSize() == 0)
487  return true;
488  FT = AT->getElementType();
489  }
490 
491  const RecordType *RT = FT->getAs<RecordType>();
492  if (!RT)
493  return false;
494 
495  // C++ record fields are never empty, at least in the Itanium ABI.
496  //
497  // FIXME: We should use a predicate for whether this behavior is true in the
498  // current ABI.
499  if (isa<CXXRecordDecl>(RT->getDecl()))
500  return false;
501 
502  return isEmptyRecord(Context, FT, AllowArrays);
503 }
504 
505 /// isEmptyRecord - Return true iff a structure contains only empty
506 /// fields. Note that a structure with a flexible array member is not
507 /// considered empty.
508 static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) {
509  const RecordType *RT = T->getAs<RecordType>();
510  if (!RT)
511  return false;
512  const RecordDecl *RD = RT->getDecl();
513  if (RD->hasFlexibleArrayMember())
514  return false;
515 
516  // If this is a C++ record, check the bases first.
517  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
518  for (const auto &I : CXXRD->bases())
519  if (!isEmptyRecord(Context, I.getType(), true))
520  return false;
521 
522  for (const auto *I : RD->fields())
523  if (!isEmptyField(Context, I, AllowArrays))
524  return false;
525  return true;
526 }
527 
528 /// isSingleElementStruct - Determine if a structure is a "single
529 /// element struct", i.e. it has exactly one non-empty field or
530 /// exactly one field which is itself a single element
531 /// struct. Structures with flexible array members are never
532 /// considered single element structs.
533 ///
534 /// \return The field declaration for the single non-empty field, if
535 /// it exists.
536 static const Type *isSingleElementStruct(QualType T, ASTContext &Context) {
537  const RecordType *RT = T->getAs<RecordType>();
538  if (!RT)
539  return nullptr;
540 
541  const RecordDecl *RD = RT->getDecl();
542  if (RD->hasFlexibleArrayMember())
543  return nullptr;
544 
545  const Type *Found = nullptr;
546 
547  // If this is a C++ record, check the bases first.
548  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
549  for (const auto &I : CXXRD->bases()) {
550  // Ignore empty records.
551  if (isEmptyRecord(Context, I.getType(), true))
552  continue;
553 
554  // If we already found an element then this isn't a single-element struct.
555  if (Found)
556  return nullptr;
557 
558  // If this is non-empty and not a single element struct, the composite
559  // cannot be a single element struct.
560  Found = isSingleElementStruct(I.getType(), Context);
561  if (!Found)
562  return nullptr;
563  }
564  }
565 
566  // Check for single element.
567  for (const auto *FD : RD->fields()) {
568  QualType FT = FD->getType();
569 
570  // Ignore empty fields.
571  if (isEmptyField(Context, FD, true))
572  continue;
573 
574  // If we already found an element then this isn't a single-element
575  // struct.
576  if (Found)
577  return nullptr;
578 
579  // Treat single element arrays as the element.
580  while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) {
581  if (AT->getSize().getZExtValue() != 1)
582  break;
583  FT = AT->getElementType();
584  }
585 
586  if (!isAggregateTypeForABI(FT)) {
587  Found = FT.getTypePtr();
588  } else {
589  Found = isSingleElementStruct(FT, Context);
590  if (!Found)
591  return nullptr;
592  }
593  }
594 
595  // We don't consider a struct a single-element struct if it has
596  // padding beyond the element type.
597  if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T))
598  return nullptr;
599 
600  return Found;
601 }
602 
603 namespace {
604 Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
605  const ABIArgInfo &AI) {
606  // This default implementation defers to the llvm backend's va_arg
607  // instruction. It can handle only passing arguments directly
608  // (typically only handled in the backend for primitive types), or
609  // aggregates passed indirectly by pointer (NOTE: if the "byval"
610  // flag has ABI impact in the callee, this implementation cannot
611  // work.)
612 
613  // Only a few cases are covered here at the moment -- those needed
614  // by the default abi.
615  llvm::Value *Val;
616 
617  if (AI.isIndirect()) {
618  assert(!AI.getPaddingType() &&
619  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
620  assert(
621  !AI.getIndirectRealign() &&
622  "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!");
623 
624  auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty);
625  CharUnits TyAlignForABI = TyInfo.second;
626 
627  llvm::Type *BaseTy =
628  llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty));
629  llvm::Value *Addr =
630  CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy);
631  return Address(Addr, TyAlignForABI);
632  } else {
633  assert((AI.isDirect() || AI.isExtend()) &&
634  "Unexpected ArgInfo Kind in generic VAArg emitter!");
635 
636  assert(!AI.getInReg() &&
637  "Unexpected InReg seen in arginfo in generic VAArg emitter!");
638  assert(!AI.getPaddingType() &&
639  "Unexpected PaddingType seen in arginfo in generic VAArg emitter!");
640  assert(!AI.getDirectOffset() &&
641  "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!");
642  assert(!AI.getCoerceToType() &&
643  "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!");
644 
645  Address Temp = CGF.CreateMemTemp(Ty, "varet");
646  Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty));
647  CGF.Builder.CreateStore(Val, Temp);
648  return Temp;
649  }
650 }
651 
652 /// DefaultABIInfo - The default implementation for ABI specific
653 /// details. This implementation provides information which results in
654 /// self-consistent and sensible LLVM IR generation, but does not
655 /// conform to any particular ABI.
656 class DefaultABIInfo : public ABIInfo {
657 public:
658  DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
659 
662 
663  void computeInfo(CGFunctionInfo &FI) const override {
664  if (!getCXXABI().classifyReturnType(FI))
666  for (auto &I : FI.arguments())
667  I.info = classifyArgumentType(I.type);
668  }
669 
670  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
671  QualType Ty) const override {
672  return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty));
673  }
674 };
675 
676 class DefaultTargetCodeGenInfo : public TargetCodeGenInfo {
677 public:
678  DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
679  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
680 };
681 
684 
685  if (isAggregateTypeForABI(Ty)) {
686  // Records with non-trivial destructors/copy-constructors should not be
687  // passed by value.
690 
691  return getNaturalAlignIndirect(Ty);
692  }
693 
694  // Treat an enum type as its underlying type.
695  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
696  Ty = EnumTy->getDecl()->getIntegerType();
697 
700 }
701 
703  if (RetTy->isVoidType())
704  return ABIArgInfo::getIgnore();
705 
706  if (isAggregateTypeForABI(RetTy))
707  return getNaturalAlignIndirect(RetTy);
708 
709  // Treat an enum type as its underlying type.
710  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
711  RetTy = EnumTy->getDecl()->getIntegerType();
712 
713  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
715 }
716 
717 //===----------------------------------------------------------------------===//
718 // WebAssembly ABI Implementation
719 //
720 // This is a very simple ABI that relies a lot on DefaultABIInfo.
721 //===----------------------------------------------------------------------===//
722 
723 class WebAssemblyABIInfo final : public SwiftABIInfo {
724  DefaultABIInfo defaultInfo;
725 
726 public:
727  explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT)
728  : SwiftABIInfo(CGT), defaultInfo(CGT) {}
729 
730 private:
733 
734  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
735  // non-virtual, but computeInfo and EmitVAArg are virtual, so we
736  // overload them.
737  void computeInfo(CGFunctionInfo &FI) const override {
738  if (!getCXXABI().classifyReturnType(FI))
740  for (auto &Arg : FI.arguments())
741  Arg.info = classifyArgumentType(Arg.type);
742  }
743 
744  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
745  QualType Ty) const override;
746 
747  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
748  bool asReturnValue) const override {
749  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
750  }
751 
752  bool isSwiftErrorInRegister() const override {
753  return false;
754  }
755 };
756 
757 class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo {
758 public:
759  explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
760  : TargetCodeGenInfo(new WebAssemblyABIInfo(CGT)) {}
761 
762  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
763  CodeGen::CodeGenModule &CGM) const override {
764  if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) {
765  llvm::Function *Fn = cast<llvm::Function>(GV);
766  if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype())
767  Fn->addFnAttr("no-prototype");
768  }
769  }
770 };
771 
772 /// Classify argument of given type \p Ty.
775 
776  if (isAggregateTypeForABI(Ty)) {
777  // Records with non-trivial destructors/copy-constructors should not be
778  // passed by value.
779  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
781  // Ignore empty structs/unions.
782  if (isEmptyRecord(getContext(), Ty, true))
783  return ABIArgInfo::getIgnore();
784  // Lower single-element structs to just pass a regular value. TODO: We
785  // could do reasonable-size multiple-element structs too, using getExpand(),
786  // though watch out for things like bitfields.
787  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
788  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
789  }
790 
791  // Otherwise just do the default thing.
792  return defaultInfo.classifyArgumentType(Ty);
793 }
794 
796  if (isAggregateTypeForABI(RetTy)) {
797  // Records with non-trivial destructors/copy-constructors should not be
798  // returned by value.
799  if (!getRecordArgABI(RetTy, getCXXABI())) {
800  // Ignore empty structs/unions.
801  if (isEmptyRecord(getContext(), RetTy, true))
802  return ABIArgInfo::getIgnore();
803  // Lower single-element structs to just return a regular value. TODO: We
804  // could do reasonable-size multiple-element structs too, using
805  // ABIArgInfo::getDirect().
806  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
807  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
808  }
809  }
810 
811  // Otherwise just do the default thing.
812  return defaultInfo.classifyReturnType(RetTy);
813 }
814 
815 Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
816  QualType Ty) const {
817  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect=*/ false,
818  getContext().getTypeInfoInChars(Ty),
820  /*AllowHigherAlign=*/ true);
821 }
822 
823 //===----------------------------------------------------------------------===//
824 // le32/PNaCl bitcode ABI Implementation
825 //
826 // This is a simplified version of the x86_32 ABI. Arguments and return values
827 // are always passed on the stack.
828 //===----------------------------------------------------------------------===//
829 
830 class PNaClABIInfo : public ABIInfo {
831  public:
832  PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
833 
836 
837  void computeInfo(CGFunctionInfo &FI) const override;
839  Address VAListAddr, QualType Ty) const override;
840 };
841 
842 class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
843  public:
844  PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
845  : TargetCodeGenInfo(new PNaClABIInfo(CGT)) {}
846 };
847 
848 void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
849  if (!getCXXABI().classifyReturnType(FI))
851 
852  for (auto &I : FI.arguments())
853  I.info = classifyArgumentType(I.type);
854 }
855 
856 Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
857  QualType Ty) const {
858  // The PNaCL ABI is a bit odd, in that varargs don't use normal
859  // function classification. Structs get passed directly for varargs
860  // functions, through a rewriting transform in
861  // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
862  // this target to actually support a va_arg instructions with an
863  // aggregate type, unlike other targets.
864  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
865 }
866 
867 /// Classify argument of given type \p Ty.
869  if (isAggregateTypeForABI(Ty)) {
872  return getNaturalAlignIndirect(Ty);
873  } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
874  // Treat an enum type as its underlying type.
875  Ty = EnumTy->getDecl()->getIntegerType();
876  } else if (Ty->isFloatingType()) {
877  // Floating-point types don't go inreg.
878  return ABIArgInfo::getDirect();
879  }
880 
883 }
884 
886  if (RetTy->isVoidType())
887  return ABIArgInfo::getIgnore();
888 
889  // In the PNaCl ABI we always return records/structures on the stack.
890  if (isAggregateTypeForABI(RetTy))
891  return getNaturalAlignIndirect(RetTy);
892 
893  // Treat an enum type as its underlying type.
894  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
895  RetTy = EnumTy->getDecl()->getIntegerType();
896 
897  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
899 }
900 
901 /// IsX86_MMXType - Return true if this is an MMX type.
902 bool IsX86_MMXType(llvm::Type *IRType) {
903  // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>.
904  return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
905  cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
906  IRType->getScalarSizeInBits() != 64;
907 }
908 
909 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
910  StringRef Constraint,
911  llvm::Type* Ty) {
912  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
913  .Cases("y", "&y", "^Ym", true)
914  .Default(false);
915  if (IsMMXCons && Ty->isVectorTy()) {
916  if (cast<llvm::VectorType>(Ty)->getBitWidth() != 64) {
917  // Invalid MMX constraint
918  return nullptr;
919  }
920 
921  return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
922  }
923 
924  // No operation needed
925  return Ty;
926 }
927 
928 /// Returns true if this type can be passed in SSE registers with the
929 /// X86_VectorCall calling convention. Shared between x86_32 and x86_64.
930 static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) {
931  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
932  if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
933  if (BT->getKind() == BuiltinType::LongDouble) {
934  if (&Context.getTargetInfo().getLongDoubleFormat() ==
935  &llvm::APFloat::x87DoubleExtended())
936  return false;
937  }
938  return true;
939  }
940  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
941  // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX
942  // registers specially.
943  unsigned VecSize = Context.getTypeSize(VT);
944  if (VecSize == 128 || VecSize == 256 || VecSize == 512)
945  return true;
946  }
947  return false;
948 }
949 
950 /// Returns true if this aggregate is small enough to be passed in SSE registers
951 /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64.
952 static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) {
953  return NumMembers <= 4;
954 }
955 
956 /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86.
957 static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) {
958  auto AI = ABIArgInfo::getDirect(T);
959  AI.setInReg(true);
960  AI.setCanBeFlattened(false);
961  return AI;
962 }
963 
964 //===----------------------------------------------------------------------===//
965 // X86-32 ABI Implementation
966 //===----------------------------------------------------------------------===//
967 
968 /// Similar to llvm::CCState, but for Clang.
969 struct CCState {
970  CCState(unsigned CC) : CC(CC), FreeRegs(0), FreeSSERegs(0) {}
971 
972  unsigned CC;
973  unsigned FreeRegs;
974  unsigned FreeSSERegs;
975 };
976 
977 enum {
978  // Vectorcall only allows the first 6 parameters to be passed in registers.
979  VectorcallMaxParamNumAsReg = 6
980 };
981 
982 /// X86_32ABIInfo - The X86-32 ABI information.
983 class X86_32ABIInfo : public SwiftABIInfo {
984  enum Class {
985  Integer,
986  Float
987  };
988 
989  static const unsigned MinABIStackAlignInBytes = 4;
990 
991  bool IsDarwinVectorABI;
992  bool IsRetSmallStructInRegABI;
993  bool IsWin32StructABI;
994  bool IsSoftFloatABI;
995  bool IsMCUABI;
996  unsigned DefaultNumRegisterParameters;
997 
998  static bool isRegisterSize(unsigned Size) {
999  return (Size == 8 || Size == 16 || Size == 32 || Size == 64);
1000  }
1001 
1002  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
1003  // FIXME: Assumes vectorcall is in use.
1004  return isX86VectorTypeForVectorCall(getContext(), Ty);
1005  }
1006 
1007  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
1008  uint64_t NumMembers) const override {
1009  // FIXME: Assumes vectorcall is in use.
1010  return isX86VectorCallAggregateSmallEnough(NumMembers);
1011  }
1012 
1013  bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const;
1014 
1015  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1016  /// such that the argument will be passed in memory.
1017  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
1018 
1019  ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const;
1020 
1021  /// Return the alignment to use for the given type on the stack.
1022  unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const;
1023 
1024  Class classify(QualType Ty) const;
1025  ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
1026  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
1027 
1028  /// Updates the number of available free registers, returns
1029  /// true if any registers were allocated.
1030  bool updateFreeRegs(QualType Ty, CCState &State) const;
1031 
1032  bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
1033  bool &NeedsPadding) const;
1034  bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
1035 
1036  bool canExpandIndirectArgument(QualType Ty) const;
1037 
1038  /// Rewrite the function info so that all memory arguments use
1039  /// inalloca.
1040  void rewriteWithInAlloca(CGFunctionInfo &FI) const;
1041 
1042  void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1043  CharUnits &StackOffset, ABIArgInfo &Info,
1044  QualType Type) const;
1045  void computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1046  bool &UsedInAlloca) const;
1047 
1048 public:
1049 
1050  void computeInfo(CGFunctionInfo &FI) const override;
1051  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
1052  QualType Ty) const override;
1053 
1054  X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1055  bool RetSmallStructInRegABI, bool Win32StructABI,
1056  unsigned NumRegisterParameters, bool SoftFloatABI)
1057  : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
1058  IsRetSmallStructInRegABI(RetSmallStructInRegABI),
1059  IsWin32StructABI(Win32StructABI),
1060  IsSoftFloatABI(SoftFloatABI),
1061  IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
1062  DefaultNumRegisterParameters(NumRegisterParameters) {}
1063 
1064  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
1065  bool asReturnValue) const override {
1066  // LLVM's x86-32 lowering currently only assigns up to three
1067  // integer registers and three fp registers. Oddly, it'll use up to
1068  // four vector registers for vectors, but those can overlap with the
1069  // scalar registers.
1070  return occupiesMoreThan(CGT, scalars, /*total*/ 3);
1071  }
1072 
1073  bool isSwiftErrorInRegister() const override {
1074  // x86-32 lowering does not support passing swifterror in a register.
1075  return false;
1076  }
1077 };
1078 
1079 class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
1080 public:
1081  X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
1082  bool RetSmallStructInRegABI, bool Win32StructABI,
1083  unsigned NumRegisterParameters, bool SoftFloatABI)
1084  : TargetCodeGenInfo(new X86_32ABIInfo(
1085  CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
1086  NumRegisterParameters, SoftFloatABI)) {}
1087 
1088  static bool isStructReturnInRegABI(
1089  const llvm::Triple &Triple, const CodeGenOptions &Opts);
1090 
1091  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
1092  CodeGen::CodeGenModule &CGM) const override;
1093 
1094  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
1095  // Darwin uses different dwarf register numbers for EH.
1096  if (CGM.getTarget().getTriple().isOSDarwin()) return 5;
1097  return 4;
1098  }
1099 
1100  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
1101  llvm::Value *Address) const override;
1102 
1103  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
1104  StringRef Constraint,
1105  llvm::Type* Ty) const override {
1106  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
1107  }
1108 
1109  void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue,
1110  std::string &Constraints,
1111  std::vector<llvm::Type *> &ResultRegTypes,
1112  std::vector<llvm::Type *> &ResultTruncRegTypes,
1113  std::vector<LValue> &ResultRegDests,
1114  std::string &AsmString,
1115  unsigned NumOutputs) const override;
1116 
1117  llvm::Constant *
1118  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
1119  unsigned Sig = (0xeb << 0) | // jmp rel8
1120  (0x06 << 8) | // .+0x08
1121  ('v' << 16) |
1122  ('2' << 24);
1123  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
1124  }
1125 
1126  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
1127  return "movl\t%ebp, %ebp"
1128  "\t\t// marker for objc_retainAutoreleaseReturnValue";
1129  }
1130 };
1131 
1132 }
1133 
1134 /// Rewrite input constraint references after adding some output constraints.
1135 /// In the case where there is one output and one input and we add one output,
1136 /// we need to replace all operand references greater than or equal to 1:
1137 /// mov $0, $1
1138 /// mov eax, $1
1139 /// The result will be:
1140 /// mov $0, $2
1141 /// mov eax, $2
1142 static void rewriteInputConstraintReferences(unsigned FirstIn,
1143  unsigned NumNewOuts,
1144  std::string &AsmString) {
1145  std::string Buf;
1146  llvm::raw_string_ostream OS(Buf);
1147  size_t Pos = 0;
1148  while (Pos < AsmString.size()) {
1149  size_t DollarStart = AsmString.find('$', Pos);
1150  if (DollarStart == std::string::npos)
1151  DollarStart = AsmString.size();
1152  size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart);
1153  if (DollarEnd == std::string::npos)
1154  DollarEnd = AsmString.size();
1155  OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
1156  Pos = DollarEnd;
1157  size_t NumDollars = DollarEnd - DollarStart;
1158  if (NumDollars % 2 != 0 && Pos < AsmString.size()) {
1159  // We have an operand reference.
1160  size_t DigitStart = Pos;
1161  size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart);
1162  if (DigitEnd == std::string::npos)
1163  DigitEnd = AsmString.size();
1164  StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
1165  unsigned OperandIndex;
1166  if (!OperandStr.getAsInteger(10, OperandIndex)) {
1167  if (OperandIndex >= FirstIn)
1168  OperandIndex += NumNewOuts;
1169  OS << OperandIndex;
1170  } else {
1171  OS << OperandStr;
1172  }
1173  Pos = DigitEnd;
1174  }
1175  }
1176  AsmString = std::move(OS.str());
1177 }
1178 
1179 /// Add output constraints for EAX:EDX because they are return registers.
1180 void X86_32TargetCodeGenInfo::addReturnRegisterOutputs(
1181  CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints,
1182  std::vector<llvm::Type *> &ResultRegTypes,
1183  std::vector<llvm::Type *> &ResultTruncRegTypes,
1184  std::vector<LValue> &ResultRegDests, std::string &AsmString,
1185  unsigned NumOutputs) const {
1186  uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType());
1187 
1188  // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is
1189  // larger.
1190  if (!Constraints.empty())
1191  Constraints += ',';
1192  if (RetWidth <= 32) {
1193  Constraints += "={eax}";
1194  ResultRegTypes.push_back(CGF.Int32Ty);
1195  } else {
1196  // Use the 'A' constraint for EAX:EDX.
1197  Constraints += "=A";
1198  ResultRegTypes.push_back(CGF.Int64Ty);
1199  }
1200 
1201  // Truncate EAX or EAX:EDX to an integer of the appropriate size.
1202  llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth);
1203  ResultTruncRegTypes.push_back(CoerceTy);
1204 
1205  // Coerce the integer by bitcasting the return slot pointer.
1206  ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(),
1207  CoerceTy->getPointerTo()));
1208  ResultRegDests.push_back(ReturnSlot);
1209 
1210  rewriteInputConstraintReferences(NumOutputs, 1, AsmString);
1211 }
1212 
1213 /// shouldReturnTypeInRegister - Determine if the given type should be
1214 /// returned in a register (for the Darwin and MCU ABI).
1215 bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
1216  ASTContext &Context) const {
1217  uint64_t Size = Context.getTypeSize(Ty);
1218 
1219  // For i386, type must be register sized.
1220  // For the MCU ABI, it only needs to be <= 8-byte
1221  if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
1222  return false;
1223 
1224  if (Ty->isVectorType()) {
1225  // 64- and 128- bit vectors inside structures are not returned in
1226  // registers.
1227  if (Size == 64 || Size == 128)
1228  return false;
1229 
1230  return true;
1231  }
1232 
1233  // If this is a builtin, pointer, enum, complex type, member pointer, or
1234  // member function pointer it is ok.
1235  if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
1236  Ty->isAnyComplexType() || Ty->isEnumeralType() ||
1237  Ty->isBlockPointerType() || Ty->isMemberPointerType())
1238  return true;
1239 
1240  // Arrays are treated like records.
1241  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty))
1242  return shouldReturnTypeInRegister(AT->getElementType(), Context);
1243 
1244  // Otherwise, it must be a record type.
1245  const RecordType *RT = Ty->getAs<RecordType>();
1246  if (!RT) return false;
1247 
1248  // FIXME: Traverse bases here too.
1249 
1250  // Structure types are passed in register if all fields would be
1251  // passed in a register.
1252  for (const auto *FD : RT->getDecl()->fields()) {
1253  // Empty fields are ignored.
1254  if (isEmptyField(Context, FD, true))
1255  continue;
1256 
1257  // Check fields recursively.
1258  if (!shouldReturnTypeInRegister(FD->getType(), Context))
1259  return false;
1260  }
1261  return true;
1262 }
1263 
1264 static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) {
1265  // Treat complex types as the element type.
1266  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
1267  Ty = CTy->getElementType();
1268 
1269  // Check for a type which we know has a simple scalar argument-passing
1270  // convention without any padding. (We're specifically looking for 32
1271  // and 64-bit integer and integer-equivalents, float, and double.)
1272  if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
1273  !Ty->isEnumeralType() && !Ty->isBlockPointerType())
1274  return false;
1275 
1276  uint64_t Size = Context.getTypeSize(Ty);
1277  return Size == 32 || Size == 64;
1278 }
1279 
1280 static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD,
1281  uint64_t &Size) {
1282  for (const auto *FD : RD->fields()) {
1283  // Scalar arguments on the stack get 4 byte alignment on x86. If the
1284  // argument is smaller than 32-bits, expanding the struct will create
1285  // alignment padding.
1286  if (!is32Or64BitBasicType(FD->getType(), Context))
1287  return false;
1288 
1289  // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
1290  // how to expand them yet, and the predicate for telling if a bitfield still
1291  // counts as "basic" is more complicated than what we were doing previously.
1292  if (FD->isBitField())
1293  return false;
1294 
1295  Size += Context.getTypeSize(FD->getType());
1296  }
1297  return true;
1298 }
1299 
1300 static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD,
1301  uint64_t &Size) {
1302  // Don't do this if there are any non-empty bases.
1303  for (const CXXBaseSpecifier &Base : RD->bases()) {
1304  if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
1305  Size))
1306  return false;
1307  }
1308  if (!addFieldSizes(Context, RD, Size))
1309  return false;
1310  return true;
1311 }
1312 
1313 /// Test whether an argument type which is to be passed indirectly (on the
1314 /// stack) would have the equivalent layout if it was expanded into separate
1315 /// arguments. If so, we prefer to do the latter to avoid inhibiting
1316 /// optimizations.
1317 bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const {
1318  // We can only expand structure types.
1319  const RecordType *RT = Ty->getAs<RecordType>();
1320  if (!RT)
1321  return false;
1322  const RecordDecl *RD = RT->getDecl();
1323  uint64_t Size = 0;
1324  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
1325  if (!IsWin32StructABI) {
1326  // On non-Windows, we have to conservatively match our old bitcode
1327  // prototypes in order to be ABI-compatible at the bitcode level.
1328  if (!CXXRD->isCLike())
1329  return false;
1330  } else {
1331  // Don't do this for dynamic classes.
1332  if (CXXRD->isDynamicClass())
1333  return false;
1334  }
1335  if (!addBaseAndFieldSizes(getContext(), CXXRD, Size))
1336  return false;
1337  } else {
1338  if (!addFieldSizes(getContext(), RD, Size))
1339  return false;
1340  }
1341 
1342  // We can do this if there was no alignment padding.
1343  return Size == getContext().getTypeSize(Ty);
1344 }
1345 
1346 ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const {
1347  // If the return value is indirect, then the hidden argument is consuming one
1348  // integer register.
1349  if (State.FreeRegs) {
1350  --State.FreeRegs;
1351  if (!IsMCUABI)
1352  return getNaturalAlignIndirectInReg(RetTy);
1353  }
1354  return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
1355 }
1356 
1358  CCState &State) const {
1359  if (RetTy->isVoidType())
1360  return ABIArgInfo::getIgnore();
1361 
1362  const Type *Base = nullptr;
1363  uint64_t NumElts = 0;
1364  if ((State.CC == llvm::CallingConv::X86_VectorCall ||
1365  State.CC == llvm::CallingConv::X86_RegCall) &&
1366  isHomogeneousAggregate(RetTy, Base, NumElts)) {
1367  // The LLVM struct type for such an aggregate should lower properly.
1368  return ABIArgInfo::getDirect();
1369  }
1370 
1371  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
1372  // On Darwin, some vectors are returned in registers.
1373  if (IsDarwinVectorABI) {
1374  uint64_t Size = getContext().getTypeSize(RetTy);
1375 
1376  // 128-bit vectors are a special case; they are returned in
1377  // registers and we need to make sure to pick a type the LLVM
1378  // backend will like.
1379  if (Size == 128)
1380  return ABIArgInfo::getDirect(llvm::VectorType::get(
1381  llvm::Type::getInt64Ty(getVMContext()), 2));
1382 
1383  // Always return in register if it fits in a general purpose
1384  // register, or if it is 64 bits and has a single element.
1385  if ((Size == 8 || Size == 16 || Size == 32) ||
1386  (Size == 64 && VT->getNumElements() == 1))
1387  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1388  Size));
1389 
1390  return getIndirectReturnResult(RetTy, State);
1391  }
1392 
1393  return ABIArgInfo::getDirect();
1394  }
1395 
1396  if (isAggregateTypeForABI(RetTy)) {
1397  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
1398  // Structures with flexible arrays are always indirect.
1399  if (RT->getDecl()->hasFlexibleArrayMember())
1400  return getIndirectReturnResult(RetTy, State);
1401  }
1402 
1403  // If specified, structs and unions are always indirect.
1404  if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
1405  return getIndirectReturnResult(RetTy, State);
1406 
1407  // Ignore empty structs/unions.
1408  if (isEmptyRecord(getContext(), RetTy, true))
1409  return ABIArgInfo::getIgnore();
1410 
1411  // Small structures which are register sized are generally returned
1412  // in a register.
1413  if (shouldReturnTypeInRegister(RetTy, getContext())) {
1414  uint64_t Size = getContext().getTypeSize(RetTy);
1415 
1416  // As a special-case, if the struct is a "single-element" struct, and
1417  // the field is of type "float" or "double", return it in a
1418  // floating-point register. (MSVC does not apply this special case.)
1419  // We apply a similar transformation for pointer types to improve the
1420  // quality of the generated IR.
1421  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
1422  if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
1423  || SeltTy->hasPointerRepresentation())
1424  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
1425 
1426  // FIXME: We should be able to narrow this integer in cases with dead
1427  // padding.
1428  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size));
1429  }
1430 
1431  return getIndirectReturnResult(RetTy, State);
1432  }
1433 
1434  // Treat an enum type as its underlying type.
1435  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
1436  RetTy = EnumTy->getDecl()->getIntegerType();
1437 
1438  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
1439  : ABIArgInfo::getDirect());
1440 }
1441 
1442 static bool isSSEVectorType(ASTContext &Context, QualType Ty) {
1443  return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128;
1444 }
1445 
1446 static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty) {
1447  const RecordType *RT = Ty->getAs<RecordType>();
1448  if (!RT)
1449  return 0;
1450  const RecordDecl *RD = RT->getDecl();
1451 
1452  // If this is a C++ record, check the bases first.
1453  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
1454  for (const auto &I : CXXRD->bases())
1455  if (!isRecordWithSSEVectorType(Context, I.getType()))
1456  return false;
1457 
1458  for (const auto *i : RD->fields()) {
1459  QualType FT = i->getType();
1460 
1461  if (isSSEVectorType(Context, FT))
1462  return true;
1463 
1464  if (isRecordWithSSEVectorType(Context, FT))
1465  return true;
1466  }
1467 
1468  return false;
1469 }
1470 
1471 unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty,
1472  unsigned Align) const {
1473  // Otherwise, if the alignment is less than or equal to the minimum ABI
1474  // alignment, just use the default; the backend will handle this.
1475  if (Align <= MinABIStackAlignInBytes)
1476  return 0; // Use default alignment.
1477 
1478  // On non-Darwin, the stack type alignment is always 4.
1479  if (!IsDarwinVectorABI) {
1480  // Set explicit alignment, since we may need to realign the top.
1481  return MinABIStackAlignInBytes;
1482  }
1483 
1484  // Otherwise, if the type contains an SSE vector type, the alignment is 16.
1485  if (Align >= 16 && (isSSEVectorType(getContext(), Ty) ||
1487  return 16;
1488 
1489  return MinABIStackAlignInBytes;
1490 }
1491 
1492 ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal,
1493  CCState &State) const {
1494  if (!ByVal) {
1495  if (State.FreeRegs) {
1496  --State.FreeRegs; // Non-byval indirects just use one pointer.
1497  if (!IsMCUABI)
1498  return getNaturalAlignIndirectInReg(Ty);
1499  }
1500  return getNaturalAlignIndirect(Ty, false);
1501  }
1502 
1503  // Compute the byval alignment.
1504  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
1505  unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign);
1506  if (StackAlign == 0)
1507  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true);
1508 
1509  // If the stack alignment is less than the type alignment, realign the
1510  // argument.
1511  bool Realign = TypeAlign > StackAlign;
1513  /*ByVal=*/true, Realign);
1514 }
1515 
1516 X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const {
1517  const Type *T = isSingleElementStruct(Ty, getContext());
1518  if (!T)
1519  T = Ty.getTypePtr();
1520 
1521  if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
1522  BuiltinType::Kind K = BT->getKind();
1523  if (K == BuiltinType::Float || K == BuiltinType::Double)
1524  return Float;
1525  }
1526  return Integer;
1527 }
1528 
1529 bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
1530  if (!IsSoftFloatABI) {
1531  Class C = classify(Ty);
1532  if (C == Float)
1533  return false;
1534  }
1535 
1536  unsigned Size = getContext().getTypeSize(Ty);
1537  unsigned SizeInRegs = (Size + 31) / 32;
1538 
1539  if (SizeInRegs == 0)
1540  return false;
1541 
1542  if (!IsMCUABI) {
1543  if (SizeInRegs > State.FreeRegs) {
1544  State.FreeRegs = 0;
1545  return false;
1546  }
1547  } else {
1548  // The MCU psABI allows passing parameters in-reg even if there are
1549  // earlier parameters that are passed on the stack. Also,
1550  // it does not allow passing >8-byte structs in-register,
1551  // even if there are 3 free registers available.
1552  if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
1553  return false;
1554  }
1555 
1556  State.FreeRegs -= SizeInRegs;
1557  return true;
1558 }
1559 
1560 bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
1561  bool &InReg,
1562  bool &NeedsPadding) const {
1563  // On Windows, aggregates other than HFAs are never passed in registers, and
1564  // they do not consume register slots. Homogenous floating-point aggregates
1565  // (HFAs) have already been dealt with at this point.
1566  if (IsWin32StructABI && isAggregateTypeForABI(Ty))
1567  return false;
1568 
1569  NeedsPadding = false;
1570  InReg = !IsMCUABI;
1571 
1572  if (!updateFreeRegs(Ty, State))
1573  return false;
1574 
1575  if (IsMCUABI)
1576  return true;
1577 
1578  if (State.CC == llvm::CallingConv::X86_FastCall ||
1579  State.CC == llvm::CallingConv::X86_VectorCall ||
1580  State.CC == llvm::CallingConv::X86_RegCall) {
1581  if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
1582  NeedsPadding = true;
1583 
1584  return false;
1585  }
1586 
1587  return true;
1588 }
1589 
1590 bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
1591  if (!updateFreeRegs(Ty, State))
1592  return false;
1593 
1594  if (IsMCUABI)
1595  return false;
1596 
1597  if (State.CC == llvm::CallingConv::X86_FastCall ||
1598  State.CC == llvm::CallingConv::X86_VectorCall ||
1599  State.CC == llvm::CallingConv::X86_RegCall) {
1600  if (getContext().getTypeSize(Ty) > 32)
1601  return false;
1602 
1603  return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
1604  Ty->isReferenceType());
1605  }
1606 
1607  return true;
1608 }
1609 
1611  CCState &State) const {
1612  // FIXME: Set alignment on indirect arguments.
1613 
1615 
1616  // Check with the C++ ABI first.
1617  const RecordType *RT = Ty->getAs<RecordType>();
1618  if (RT) {
1620  if (RAA == CGCXXABI::RAA_Indirect) {
1621  return getIndirectResult(Ty, false, State);
1622  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
1623  // The field index doesn't matter, we'll fix it up later.
1624  return ABIArgInfo::getInAlloca(/*FieldIndex=*/0);
1625  }
1626  }
1627 
1628  // Regcall uses the concept of a homogenous vector aggregate, similar
1629  // to other targets.
1630  const Type *Base = nullptr;
1631  uint64_t NumElts = 0;
1632  if (State.CC == llvm::CallingConv::X86_RegCall &&
1633  isHomogeneousAggregate(Ty, Base, NumElts)) {
1634 
1635  if (State.FreeSSERegs >= NumElts) {
1636  State.FreeSSERegs -= NumElts;
1637  if (Ty->isBuiltinType() || Ty->isVectorType())
1638  return ABIArgInfo::getDirect();
1639  return ABIArgInfo::getExpand();
1640  }
1641  return getIndirectResult(Ty, /*ByVal=*/false, State);
1642  }
1643 
1644  if (isAggregateTypeForABI(Ty)) {
1645  // Structures with flexible arrays are always indirect.
1646  // FIXME: This should not be byval!
1647  if (RT && RT->getDecl()->hasFlexibleArrayMember())
1648  return getIndirectResult(Ty, true, State);
1649 
1650  // Ignore empty structs/unions on non-Windows.
1651  if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true))
1652  return ABIArgInfo::getIgnore();
1653 
1654  llvm::LLVMContext &LLVMContext = getVMContext();
1655  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
1656  bool NeedsPadding = false;
1657  bool InReg;
1658  if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
1659  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
1660  SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32);
1661  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
1662  if (InReg)
1663  return ABIArgInfo::getDirectInReg(Result);
1664  else
1665  return ABIArgInfo::getDirect(Result);
1666  }
1667  llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr;
1668 
1669  // Expand small (<= 128-bit) record types when we know that the stack layout
1670  // of those arguments will match the struct. This is important because the
1671  // LLVM backend isn't smart enough to remove byval, which inhibits many
1672  // optimizations.
1673  // Don't do this for the MCU if there are still free integer registers
1674  // (see X86_64 ABI for full explanation).
1675  if (getContext().getTypeSize(Ty) <= 4 * 32 &&
1676  (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty))
1678  State.CC == llvm::CallingConv::X86_FastCall ||
1679  State.CC == llvm::CallingConv::X86_VectorCall ||
1680  State.CC == llvm::CallingConv::X86_RegCall,
1681  PaddingType);
1682 
1683  return getIndirectResult(Ty, true, State);
1684  }
1685 
1686  if (const VectorType *VT = Ty->getAs<VectorType>()) {
1687  // On Darwin, some vectors are passed in memory, we handle this by passing
1688  // it as an i8/i16/i32/i64.
1689  if (IsDarwinVectorABI) {
1690  uint64_t Size = getContext().getTypeSize(Ty);
1691  if ((Size == 8 || Size == 16 || Size == 32) ||
1692  (Size == 64 && VT->getNumElements() == 1))
1693  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
1694  Size));
1695  }
1696 
1697  if (IsX86_MMXType(CGT.ConvertType(Ty)))
1698  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64));
1699 
1700  return ABIArgInfo::getDirect();
1701  }
1702 
1703 
1704  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
1705  Ty = EnumTy->getDecl()->getIntegerType();
1706 
1707  bool InReg = shouldPrimitiveUseInReg(Ty, State);
1708 
1709  if (Ty->isPromotableIntegerType()) {
1710  if (InReg)
1711  return ABIArgInfo::getExtendInReg(Ty);
1712  return ABIArgInfo::getExtend(Ty);
1713  }
1714 
1715  if (InReg)
1716  return ABIArgInfo::getDirectInReg();
1717  return ABIArgInfo::getDirect();
1718 }
1719 
1720 void X86_32ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI, CCState &State,
1721  bool &UsedInAlloca) const {
1722  // Vectorcall x86 works subtly different than in x64, so the format is
1723  // a bit different than the x64 version. First, all vector types (not HVAs)
1724  // are assigned, with the first 6 ending up in the YMM0-5 or XMM0-5 registers.
1725  // This differs from the x64 implementation, where the first 6 by INDEX get
1726  // registers.
1727  // After that, integers AND HVAs are assigned Left to Right in the same pass.
1728  // Integers are passed as ECX/EDX if one is available (in order). HVAs will
1729  // first take up the remaining YMM/XMM registers. If insufficient registers
1730  // remain but an integer register (ECX/EDX) is available, it will be passed
1731  // in that, else, on the stack.
1732  for (auto &I : FI.arguments()) {
1733  // First pass do all the vector types.
1734  const Type *Base = nullptr;
1735  uint64_t NumElts = 0;
1736  const QualType& Ty = I.type;
1737  if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
1738  isHomogeneousAggregate(Ty, Base, NumElts)) {
1739  if (State.FreeSSERegs >= NumElts) {
1740  State.FreeSSERegs -= NumElts;
1741  I.info = ABIArgInfo::getDirect();
1742  } else {
1743  I.info = classifyArgumentType(Ty, State);
1744  }
1745  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1746  }
1747  }
1748 
1749  for (auto &I : FI.arguments()) {
1750  // Second pass, do the rest!
1751  const Type *Base = nullptr;
1752  uint64_t NumElts = 0;
1753  const QualType& Ty = I.type;
1754  bool IsHva = isHomogeneousAggregate(Ty, Base, NumElts);
1755 
1756  if (IsHva && !Ty->isVectorType() && !Ty->isBuiltinType()) {
1757  // Assign true HVAs (non vector/native FP types).
1758  if (State.FreeSSERegs >= NumElts) {
1759  State.FreeSSERegs -= NumElts;
1760  I.info = getDirectX86Hva();
1761  } else {
1762  I.info = getIndirectResult(Ty, /*ByVal=*/false, State);
1763  }
1764  } else if (!IsHva) {
1765  // Assign all Non-HVAs, so this will exclude Vector/FP args.
1766  I.info = classifyArgumentType(Ty, State);
1767  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1768  }
1769  }
1770 }
1771 
1772 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
1773  CCState State(FI.getCallingConvention());
1774  if (IsMCUABI)
1775  State.FreeRegs = 3;
1776  else if (State.CC == llvm::CallingConv::X86_FastCall)
1777  State.FreeRegs = 2;
1778  else if (State.CC == llvm::CallingConv::X86_VectorCall) {
1779  State.FreeRegs = 2;
1780  State.FreeSSERegs = 6;
1781  } else if (FI.getHasRegParm())
1782  State.FreeRegs = FI.getRegParm();
1783  else if (State.CC == llvm::CallingConv::X86_RegCall) {
1784  State.FreeRegs = 5;
1785  State.FreeSSERegs = 8;
1786  } else
1787  State.FreeRegs = DefaultNumRegisterParameters;
1788 
1789  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
1791  } else if (FI.getReturnInfo().isIndirect()) {
1792  // The C++ ABI is not aware of register usage, so we have to check if the
1793  // return value was sret and put it in a register ourselves if appropriate.
1794  if (State.FreeRegs) {
1795  --State.FreeRegs; // The sret parameter consumes a register.
1796  if (!IsMCUABI)
1797  FI.getReturnInfo().setInReg(true);
1798  }
1799  }
1800 
1801  // The chain argument effectively gives us another free register.
1802  if (FI.isChainCall())
1803  ++State.FreeRegs;
1804 
1805  bool UsedInAlloca = false;
1806  if (State.CC == llvm::CallingConv::X86_VectorCall) {
1807  computeVectorCallArgs(FI, State, UsedInAlloca);
1808  } else {
1809  // If not vectorcall, revert to normal behavior.
1810  for (auto &I : FI.arguments()) {
1811  I.info = classifyArgumentType(I.type, State);
1812  UsedInAlloca |= (I.info.getKind() == ABIArgInfo::InAlloca);
1813  }
1814  }
1815 
1816  // If we needed to use inalloca for any argument, do a second pass and rewrite
1817  // all the memory arguments to use inalloca.
1818  if (UsedInAlloca)
1819  rewriteWithInAlloca(FI);
1820 }
1821 
1822 void
1823 X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields,
1824  CharUnits &StackOffset, ABIArgInfo &Info,
1825  QualType Type) const {
1826  // Arguments are always 4-byte-aligned.
1827  CharUnits FieldAlign = CharUnits::fromQuantity(4);
1828 
1829  assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct");
1830  Info = ABIArgInfo::getInAlloca(FrameFields.size());
1831  FrameFields.push_back(CGT.ConvertTypeForMem(Type));
1832  StackOffset += getContext().getTypeSizeInChars(Type);
1833 
1834  // Insert padding bytes to respect alignment.
1835  CharUnits FieldEnd = StackOffset;
1836  StackOffset = FieldEnd.alignTo(FieldAlign);
1837  if (StackOffset != FieldEnd) {
1838  CharUnits NumBytes = StackOffset - FieldEnd;
1839  llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext());
1840  Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity());
1841  FrameFields.push_back(Ty);
1842  }
1843 }
1844 
1845 static bool isArgInAlloca(const ABIArgInfo &Info) {
1846  // Leave ignored and inreg arguments alone.
1847  switch (Info.getKind()) {
1848  case ABIArgInfo::InAlloca:
1849  return true;
1850  case ABIArgInfo::Indirect:
1851  assert(Info.getIndirectByVal());
1852  return true;
1853  case ABIArgInfo::Ignore:
1854  return false;
1855  case ABIArgInfo::Direct:
1856  case ABIArgInfo::Extend:
1857  if (Info.getInReg())
1858  return false;
1859  return true;
1860  case ABIArgInfo::Expand:
1862  // These are aggregate types which are never passed in registers when
1863  // inalloca is involved.
1864  return true;
1865  }
1866  llvm_unreachable("invalid enum");
1867 }
1868 
1869 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1870  assert(IsWin32StructABI && "inalloca only supported on win32");
1871 
1872  // Build a packed struct type for all of the arguments in memory.
1873  SmallVector<llvm::Type *, 6> FrameFields;
1874 
1875  // The stack alignment is always 4.
1876  CharUnits StackAlign = CharUnits::fromQuantity(4);
1877 
1878  CharUnits StackOffset;
1879  CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1880 
1881  // Put 'this' into the struct before 'sret', if necessary.
1882  bool IsThisCall =
1883  FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1884  ABIArgInfo &Ret = FI.getReturnInfo();
1885  if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall &&
1886  isArgInAlloca(I->info)) {
1887  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1888  ++I;
1889  }
1890 
1891  // Put the sret parameter into the inalloca struct if it's in memory.
1892  if (Ret.isIndirect() && !Ret.getInReg()) {
1894  addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy);
1895  // On Windows, the hidden sret parameter is always returned in eax.
1896  Ret.setInAllocaSRet(IsWin32StructABI);
1897  }
1898 
1899  // Skip the 'this' parameter in ecx.
1900  if (IsThisCall)
1901  ++I;
1902 
1903  // Put arguments passed in memory into the struct.
1904  for (; I != E; ++I) {
1905  if (isArgInAlloca(I->info))
1906  addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1907  }
1908 
1909  FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1910  /*isPacked=*/true),
1911  StackAlign);
1912 }
1913 
1914 Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF,
1915  Address VAListAddr, QualType Ty) const {
1916 
1917  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
1918 
1919  // x86-32 changes the alignment of certain arguments on the stack.
1920  //
1921  // Just messing with TypeInfo like this works because we never pass
1922  // anything indirectly.
1924  getTypeStackAlignInBytes(Ty, TypeInfo.second.getQuantity()));
1925 
1926  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
1928  /*AllowHigherAlign*/ true);
1929 }
1930 
1931 bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
1932  const llvm::Triple &Triple, const CodeGenOptions &Opts) {
1933  assert(Triple.getArch() == llvm::Triple::x86);
1934 
1935  switch (Opts.getStructReturnConvention()) {
1937  break;
1938  case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1939  return false;
1940  case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1941  return true;
1942  }
1943 
1944  if (Triple.isOSDarwin() || Triple.isOSIAMCU())
1945  return true;
1946 
1947  switch (Triple.getOS()) {
1948  case llvm::Triple::DragonFly:
1949  case llvm::Triple::FreeBSD:
1950  case llvm::Triple::OpenBSD:
1951  case llvm::Triple::Win32:
1952  return true;
1953  default:
1954  return false;
1955  }
1956 }
1957 
1958 void X86_32TargetCodeGenInfo::setTargetAttributes(
1959  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
1960  if (GV->isDeclaration())
1961  return;
1962  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
1963  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1964  llvm::Function *Fn = cast<llvm::Function>(GV);
1965  Fn->addFnAttr("stackrealign");
1966  }
1967  if (FD->hasAttr<AnyX86InterruptAttr>()) {
1968  llvm::Function *Fn = cast<llvm::Function>(GV);
1969  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1970  }
1971  }
1972 }
1973 
1974 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
1976  llvm::Value *Address) const {
1977  CodeGen::CGBuilderTy &Builder = CGF.Builder;
1978 
1979  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
1980 
1981  // 0-7 are the eight integer registers; the order is different
1982  // on Darwin (for EH), but the range is the same.
1983  // 8 is %eip.
1984  AssignToArrayRange(Builder, Address, Four8, 0, 8);
1985 
1986  if (CGF.CGM.getTarget().getTriple().isOSDarwin()) {
1987  // 12-16 are st(0..4). Not sure why we stop at 4.
1988  // These have size 16, which is sizeof(long double) on
1989  // platforms with 8-byte alignment for that type.
1990  llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16);
1991  AssignToArrayRange(Builder, Address, Sixteen8, 12, 16);
1992 
1993  } else {
1994  // 9 is %eflags, which doesn't get a size on Darwin for some
1995  // reason.
1996  Builder.CreateAlignedStore(
1997  Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9),
1998  CharUnits::One());
1999 
2000  // 11-16 are st(0..5). Not sure why we stop at 5.
2001  // These have size 12, which is sizeof(long double) on
2002  // platforms with 4-byte alignment for that type.
2003  llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12);
2004  AssignToArrayRange(Builder, Address, Twelve8, 11, 16);
2005  }
2006 
2007  return false;
2008 }
2009 
2010 //===----------------------------------------------------------------------===//
2011 // X86-64 ABI Implementation
2012 //===----------------------------------------------------------------------===//
2013 
2014 
2015 namespace {
2016 /// The AVX ABI level for X86 targets.
2017 enum class X86AVXABILevel {
2018  None,
2019  AVX,
2020  AVX512
2021 };
2022 
2023 /// \p returns the size in bits of the largest (native) vector for \p AVXLevel.
2024 static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) {
2025  switch (AVXLevel) {
2026  case X86AVXABILevel::AVX512:
2027  return 512;
2028  case X86AVXABILevel::AVX:
2029  return 256;
2030  case X86AVXABILevel::None:
2031  return 128;
2032  }
2033  llvm_unreachable("Unknown AVXLevel");
2034 }
2035 
2036 /// X86_64ABIInfo - The X86_64 ABI information.
2037 class X86_64ABIInfo : public SwiftABIInfo {
2038  enum Class {
2039  Integer = 0,
2040  SSE,
2041  SSEUp,
2042  X87,
2043  X87Up,
2044  ComplexX87,
2045  NoClass,
2046  Memory
2047  };
2048 
2049  /// merge - Implement the X86_64 ABI merging algorithm.
2050  ///
2051  /// Merge an accumulating classification \arg Accum with a field
2052  /// classification \arg Field.
2053  ///
2054  /// \param Accum - The accumulating classification. This should
2055  /// always be either NoClass or the result of a previous merge
2056  /// call. In addition, this should never be Memory (the caller
2057  /// should just return Memory for the aggregate).
2058  static Class merge(Class Accum, Class Field);
2059 
2060  /// postMerge - Implement the X86_64 ABI post merging algorithm.
2061  ///
2062  /// Post merger cleanup, reduces a malformed Hi and Lo pair to
2063  /// final MEMORY or SSE classes when necessary.
2064  ///
2065  /// \param AggregateSize - The size of the current aggregate in
2066  /// the classification process.
2067  ///
2068  /// \param Lo - The classification for the parts of the type
2069  /// residing in the low word of the containing object.
2070  ///
2071  /// \param Hi - The classification for the parts of the type
2072  /// residing in the higher words of the containing object.
2073  ///
2074  void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
2075 
2076  /// classify - Determine the x86_64 register classes in which the
2077  /// given type T should be passed.
2078  ///
2079  /// \param Lo - The classification for the parts of the type
2080  /// residing in the low word of the containing object.
2081  ///
2082  /// \param Hi - The classification for the parts of the type
2083  /// residing in the high word of the containing object.
2084  ///
2085  /// \param OffsetBase - The bit offset of this type in the
2086  /// containing object. Some parameters are classified different
2087  /// depending on whether they straddle an eightbyte boundary.
2088  ///
2089  /// \param isNamedArg - Whether the argument in question is a "named"
2090  /// argument, as used in AMD64-ABI 3.5.7.
2091  ///
2092  /// If a word is unused its result will be NoClass; if a type should
2093  /// be passed in Memory then at least the classification of \arg Lo
2094  /// will be Memory.
2095  ///
2096  /// The \arg Lo class will be NoClass iff the argument is ignored.
2097  ///
2098  /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
2099  /// also be ComplexX87.
2100  void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
2101  bool isNamedArg) const;
2102 
2103  llvm::Type *GetByteVectorType(QualType Ty) const;
2104  llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType,
2105  unsigned IROffset, QualType SourceTy,
2106  unsigned SourceOffset) const;
2107  llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType,
2108  unsigned IROffset, QualType SourceTy,
2109  unsigned SourceOffset) const;
2110 
2111  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2112  /// such that the argument will be returned in memory.
2113  ABIArgInfo getIndirectReturnResult(QualType Ty) const;
2114 
2115  /// getIndirectResult - Give a source type \arg Ty, return a suitable result
2116  /// such that the argument will be passed in memory.
2117  ///
2118  /// \param freeIntRegs - The number of free integer registers remaining
2119  /// available.
2120  ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const;
2121 
2122  ABIArgInfo classifyReturnType(QualType RetTy) const;
2123 
2124  ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs,
2125  unsigned &neededInt, unsigned &neededSSE,
2126  bool isNamedArg) const;
2127 
2128  ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt,
2129  unsigned &NeededSSE) const;
2130 
2131  ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
2132  unsigned &NeededSSE) const;
2133 
2134  bool IsIllegalVectorType(QualType Ty) const;
2135 
2136  /// The 0.98 ABI revision clarified a lot of ambiguities,
2137  /// unfortunately in ways that were not always consistent with
2138  /// certain previous compilers. In particular, platforms which
2139  /// required strict binary compatibility with older versions of GCC
2140  /// may need to exempt themselves.
2141  bool honorsRevision0_98() const {
2142  return !getTarget().getTriple().isOSDarwin();
2143  }
2144 
2145  /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
2146  /// classify it as INTEGER (for compatibility with older clang compilers).
2147  bool classifyIntegerMMXAsSSE() const {
2148  // Clang <= 3.8 did not do this.
2149  if (getContext().getLangOpts().getClangABICompat() <=
2151  return false;
2152 
2153  const llvm::Triple &Triple = getTarget().getTriple();
2154  if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4)
2155  return false;
2156  if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10)
2157  return false;
2158  return true;
2159  }
2160 
2161  X86AVXABILevel AVXLevel;
2162  // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on
2163  // 64-bit hardware.
2164  bool Has64BitPointers;
2165 
2166 public:
2167  X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) :
2168  SwiftABIInfo(CGT), AVXLevel(AVXLevel),
2169  Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) {
2170  }
2171 
2172  bool isPassedUsingAVXType(QualType type) const {
2173  unsigned neededInt, neededSSE;
2174  // The freeIntRegs argument doesn't matter here.
2175  ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE,
2176  /*isNamedArg*/true);
2177  if (info.isDirect()) {
2178  llvm::Type *ty = info.getCoerceToType();
2179  if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty))
2180  return (vectorTy->getBitWidth() > 128);
2181  }
2182  return false;
2183  }
2184 
2185  void computeInfo(CGFunctionInfo &FI) const override;
2186 
2187  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2188  QualType Ty) const override;
2189  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
2190  QualType Ty) const override;
2191 
2192  bool has64BitPointers() const {
2193  return Has64BitPointers;
2194  }
2195 
2196  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
2197  bool asReturnValue) const override {
2198  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2199  }
2200  bool isSwiftErrorInRegister() const override {
2201  return true;
2202  }
2203 };
2204 
2205 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
2206 class WinX86_64ABIInfo : public SwiftABIInfo {
2207 public:
2208  WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT)
2209  : SwiftABIInfo(CGT),
2210  IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {}
2211 
2212  void computeInfo(CGFunctionInfo &FI) const override;
2213 
2214  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
2215  QualType Ty) const override;
2216 
2217  bool isHomogeneousAggregateBaseType(QualType Ty) const override {
2218  // FIXME: Assumes vectorcall is in use.
2219  return isX86VectorTypeForVectorCall(getContext(), Ty);
2220  }
2221 
2222  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
2223  uint64_t NumMembers) const override {
2224  // FIXME: Assumes vectorcall is in use.
2225  return isX86VectorCallAggregateSmallEnough(NumMembers);
2226  }
2227 
2228  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars,
2229  bool asReturnValue) const override {
2230  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
2231  }
2232 
2233  bool isSwiftErrorInRegister() const override {
2234  return true;
2235  }
2236 
2237 private:
2238  ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType,
2239  bool IsVectorCall, bool IsRegCall) const;
2240  ABIArgInfo reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
2241  const ABIArgInfo &current) const;
2242  void computeVectorCallArgs(CGFunctionInfo &FI, unsigned FreeSSERegs,
2243  bool IsVectorCall, bool IsRegCall) const;
2244 
2245  bool IsMingw64;
2246 };
2247 
2248 class X86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2249 public:
2250  X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2251  : TargetCodeGenInfo(new X86_64ABIInfo(CGT, AVXLevel)) {}
2252 
2253  const X86_64ABIInfo &getABIInfo() const {
2254  return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo());
2255  }
2256 
2257  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2258  return 7;
2259  }
2260 
2261  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2262  llvm::Value *Address) const override {
2263  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2264 
2265  // 0-15 are the 16 integer registers.
2266  // 16 is %rip.
2267  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2268  return false;
2269  }
2270 
2271  llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
2272  StringRef Constraint,
2273  llvm::Type* Ty) const override {
2274  return X86AdjustInlineAsmType(CGF, Constraint, Ty);
2275  }
2276 
2277  bool isNoProtoCallVariadic(const CallArgList &args,
2278  const FunctionNoProtoType *fnType) const override {
2279  // The default CC on x86-64 sets %al to the number of SSA
2280  // registers used, and GCC sets this when calling an unprototyped
2281  // function, so we override the default behavior. However, don't do
2282  // that when AVX types are involved: the ABI explicitly states it is
2283  // undefined, and it doesn't work in practice because of how the ABI
2284  // defines varargs anyway.
2285  if (fnType->getCallConv() == CC_C) {
2286  bool HasAVXType = false;
2287  for (CallArgList::const_iterator
2288  it = args.begin(), ie = args.end(); it != ie; ++it) {
2289  if (getABIInfo().isPassedUsingAVXType(it->Ty)) {
2290  HasAVXType = true;
2291  break;
2292  }
2293  }
2294 
2295  if (!HasAVXType)
2296  return true;
2297  }
2298 
2299  return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType);
2300  }
2301 
2302  llvm::Constant *
2303  getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override {
2304  unsigned Sig = (0xeb << 0) | // jmp rel8
2305  (0x06 << 8) | // .+0x08
2306  ('v' << 16) |
2307  ('2' << 24);
2308  return llvm::ConstantInt::get(CGM.Int32Ty, Sig);
2309  }
2310 
2311  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2312  CodeGen::CodeGenModule &CGM) const override {
2313  if (GV->isDeclaration())
2314  return;
2315  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2316  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2317  llvm::Function *Fn = cast<llvm::Function>(GV);
2318  Fn->addFnAttr("stackrealign");
2319  }
2320  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2321  llvm::Function *Fn = cast<llvm::Function>(GV);
2322  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2323  }
2324  }
2325  }
2326 };
2327 
2328 class PS4TargetCodeGenInfo : public X86_64TargetCodeGenInfo {
2329 public:
2330  PS4TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel)
2331  : X86_64TargetCodeGenInfo(CGT, AVXLevel) {}
2332 
2333  void getDependentLibraryOption(llvm::StringRef Lib,
2334  llvm::SmallString<24> &Opt) const override {
2335  Opt = "\01";
2336  // If the argument contains a space, enclose it in quotes.
2337  if (Lib.find(" ") != StringRef::npos)
2338  Opt += "\"" + Lib.str() + "\"";
2339  else
2340  Opt += Lib;
2341  }
2342 };
2343 
2344 static std::string qualifyWindowsLibrary(llvm::StringRef Lib) {
2345  // If the argument does not end in .lib, automatically add the suffix.
2346  // If the argument contains a space, enclose it in quotes.
2347  // This matches the behavior of MSVC.
2348  bool Quote = (Lib.find(" ") != StringRef::npos);
2349  std::string ArgStr = Quote ? "\"" : "";
2350  ArgStr += Lib;
2351  if (!Lib.endswith_lower(".lib") && !Lib.endswith_lower(".a"))
2352  ArgStr += ".lib";
2353  ArgStr += Quote ? "\"" : "";
2354  return ArgStr;
2355 }
2356 
2357 class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
2358 public:
2359  WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2360  bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
2361  unsigned NumRegisterParameters)
2362  : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
2363  Win32StructABI, NumRegisterParameters, false) {}
2364 
2365  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2366  CodeGen::CodeGenModule &CGM) const override;
2367 
2368  void getDependentLibraryOption(llvm::StringRef Lib,
2369  llvm::SmallString<24> &Opt) const override {
2370  Opt = "/DEFAULTLIB:";
2371  Opt += qualifyWindowsLibrary(Lib);
2372  }
2373 
2374  void getDetectMismatchOption(llvm::StringRef Name,
2375  llvm::StringRef Value,
2376  llvm::SmallString<32> &Opt) const override {
2377  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2378  }
2379 };
2380 
2381 static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2382  CodeGen::CodeGenModule &CGM) {
2383  if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) {
2384 
2385  if (CGM.getCodeGenOpts().StackProbeSize != 4096)
2386  Fn->addFnAttr("stack-probe-size",
2387  llvm::utostr(CGM.getCodeGenOpts().StackProbeSize));
2388  if (CGM.getCodeGenOpts().NoStackArgProbe)
2389  Fn->addFnAttr("no-stack-arg-probe");
2390  }
2391 }
2392 
2393 void WinX86_32TargetCodeGenInfo::setTargetAttributes(
2394  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2395  X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
2396  if (GV->isDeclaration())
2397  return;
2398  addStackProbeTargetAttributes(D, GV, CGM);
2399 }
2400 
2401 class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo {
2402 public:
2403  WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
2404  X86AVXABILevel AVXLevel)
2405  : TargetCodeGenInfo(new WinX86_64ABIInfo(CGT)) {}
2406 
2407  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
2408  CodeGen::CodeGenModule &CGM) const override;
2409 
2410  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
2411  return 7;
2412  }
2413 
2414  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
2415  llvm::Value *Address) const override {
2416  llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8);
2417 
2418  // 0-15 are the 16 integer registers.
2419  // 16 is %rip.
2420  AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16);
2421  return false;
2422  }
2423 
2424  void getDependentLibraryOption(llvm::StringRef Lib,
2425  llvm::SmallString<24> &Opt) const override {
2426  Opt = "/DEFAULTLIB:";
2427  Opt += qualifyWindowsLibrary(Lib);
2428  }
2429 
2430  void getDetectMismatchOption(llvm::StringRef Name,
2431  llvm::StringRef Value,
2432  llvm::SmallString<32> &Opt) const override {
2433  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
2434  }
2435 };
2436 
2437 void WinX86_64TargetCodeGenInfo::setTargetAttributes(
2438  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
2440  if (GV->isDeclaration())
2441  return;
2442  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
2443  if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
2444  llvm::Function *Fn = cast<llvm::Function>(GV);
2445  Fn->addFnAttr("stackrealign");
2446  }
2447  if (FD->hasAttr<AnyX86InterruptAttr>()) {
2448  llvm::Function *Fn = cast<llvm::Function>(GV);
2449  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
2450  }
2451  }
2452 
2453  addStackProbeTargetAttributes(D, GV, CGM);
2454 }
2455 }
2456 
2457 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
2458  Class &Hi) const {
2459  // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
2460  //
2461  // (a) If one of the classes is Memory, the whole argument is passed in
2462  // memory.
2463  //
2464  // (b) If X87UP is not preceded by X87, the whole argument is passed in
2465  // memory.
2466  //
2467  // (c) If the size of the aggregate exceeds two eightbytes and the first
2468  // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
2469  // argument is passed in memory. NOTE: This is necessary to keep the
2470  // ABI working for processors that don't support the __m256 type.
2471  //
2472  // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
2473  //
2474  // Some of these are enforced by the merging logic. Others can arise
2475  // only with unions; for example:
2476  // union { _Complex double; unsigned; }
2477  //
2478  // Note that clauses (b) and (c) were added in 0.98.
2479  //
2480  if (Hi == Memory)
2481  Lo = Memory;
2482  if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
2483  Lo = Memory;
2484  if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
2485  Lo = Memory;
2486  if (Hi == SSEUp && Lo != SSE)
2487  Hi = SSE;
2488 }
2489 
2490 X86_64ABIInfo::Class X86_64ABIInfo::merge(Class Accum, Class Field) {
2491  // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
2492  // classified recursively so that always two fields are
2493  // considered. The resulting class is calculated according to
2494  // the classes of the fields in the eightbyte:
2495  //
2496  // (a) If both classes are equal, this is the resulting class.
2497  //
2498  // (b) If one of the classes is NO_CLASS, the resulting class is
2499  // the other class.
2500  //
2501  // (c) If one of the classes is MEMORY, the result is the MEMORY
2502  // class.
2503  //
2504  // (d) If one of the classes is INTEGER, the result is the
2505  // INTEGER.
2506  //
2507  // (e) If one of the classes is X87, X87UP, COMPLEX_X87 class,
2508  // MEMORY is used as class.
2509  //
2510  // (f) Otherwise class SSE is used.
2511 
2512  // Accum should never be memory (we should have returned) or
2513  // ComplexX87 (because this cannot be passed in a structure).
2514  assert((Accum != Memory && Accum != ComplexX87) &&
2515  "Invalid accumulated classification during merge.");
2516  if (Accum == Field || Field == NoClass)
2517  return Accum;
2518  if (Field == Memory)
2519  return Memory;
2520  if (Accum == NoClass)
2521  return Field;
2522  if (Accum == Integer || Field == Integer)
2523  return Integer;
2524  if (Field == X87 || Field == X87Up || Field == ComplexX87 ||
2525  Accum == X87 || Accum == X87Up)
2526  return Memory;
2527  return SSE;
2528 }
2529 
2530 void X86_64ABIInfo::classify(QualType Ty, uint64_t OffsetBase,
2531  Class &Lo, Class &Hi, bool isNamedArg) const {
2532  // FIXME: This code can be simplified by introducing a simple value class for
2533  // Class pairs with appropriate constructor methods for the various
2534  // situations.
2535 
2536  // FIXME: Some of the split computations are wrong; unaligned vectors
2537  // shouldn't be passed in registers for example, so there is no chance they
2538  // can straddle an eightbyte. Verify & simplify.
2539 
2540  Lo = Hi = NoClass;
2541 
2542  Class &Current = OffsetBase < 64 ? Lo : Hi;
2543  Current = Memory;
2544 
2545  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
2546  BuiltinType::Kind k = BT->getKind();
2547 
2548  if (k == BuiltinType::Void) {
2549  Current = NoClass;
2550  } else if (k == BuiltinType::Int128 || k == BuiltinType::UInt128) {
2551  Lo = Integer;
2552  Hi = Integer;
2553  } else if (k >= BuiltinType::Bool && k <= BuiltinType::LongLong) {
2554  Current = Integer;
2555  } else if (k == BuiltinType::Float || k == BuiltinType::Double) {
2556  Current = SSE;
2557  } else if (k == BuiltinType::LongDouble) {
2558  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2559  if (LDF == &llvm::APFloat::IEEEquad()) {
2560  Lo = SSE;
2561  Hi = SSEUp;
2562  } else if (LDF == &llvm::APFloat::x87DoubleExtended()) {
2563  Lo = X87;
2564  Hi = X87Up;
2565  } else if (LDF == &llvm::APFloat::IEEEdouble()) {
2566  Current = SSE;
2567  } else
2568  llvm_unreachable("unexpected long double representation!");
2569  }
2570  // FIXME: _Decimal32 and _Decimal64 are SSE.
2571  // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
2572  return;
2573  }
2574 
2575  if (const EnumType *ET = Ty->getAs<EnumType>()) {
2576  // Classify the underlying integer type.
2577  classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
2578  return;
2579  }
2580 
2581  if (Ty->hasPointerRepresentation()) {
2582  Current = Integer;
2583  return;
2584  }
2585 
2586  if (Ty->isMemberPointerType()) {
2587  if (Ty->isMemberFunctionPointerType()) {
2588  if (Has64BitPointers) {
2589  // If Has64BitPointers, this is an {i64, i64}, so classify both
2590  // Lo and Hi now.
2591  Lo = Hi = Integer;
2592  } else {
2593  // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
2594  // straddles an eightbyte boundary, Hi should be classified as well.
2595  uint64_t EB_FuncPtr = (OffsetBase) / 64;
2596  uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
2597  if (EB_FuncPtr != EB_ThisAdj) {
2598  Lo = Hi = Integer;
2599  } else {
2600  Current = Integer;
2601  }
2602  }
2603  } else {
2604  Current = Integer;
2605  }
2606  return;
2607  }
2608 
2609  if (const VectorType *VT = Ty->getAs<VectorType>()) {
2610  uint64_t Size = getContext().getTypeSize(VT);
2611  if (Size == 1 || Size == 8 || Size == 16 || Size == 32) {
2612  // gcc passes the following as integer:
2613  // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
2614  // 2 bytes - <2 x char>, <1 x short>
2615  // 1 byte - <1 x char>
2616  Current = Integer;
2617 
2618  // If this type crosses an eightbyte boundary, it should be
2619  // split.
2620  uint64_t EB_Lo = (OffsetBase) / 64;
2621  uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
2622  if (EB_Lo != EB_Hi)
2623  Hi = Lo;
2624  } else if (Size == 64) {
2625  QualType ElementType = VT->getElementType();
2626 
2627  // gcc passes <1 x double> in memory. :(
2628  if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
2629  return;
2630 
2631  // gcc passes <1 x long long> as SSE but clang used to unconditionally
2632  // pass them as integer. For platforms where clang is the de facto
2633  // platform compiler, we must continue to use integer.
2634  if (!classifyIntegerMMXAsSSE() &&
2635  (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
2636  ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
2637  ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
2638  ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
2639  Current = Integer;
2640  else
2641  Current = SSE;
2642 
2643  // If this type crosses an eightbyte boundary, it should be
2644  // split.
2645  if (OffsetBase && OffsetBase != 64)
2646  Hi = Lo;
2647  } else if (Size == 128 ||
2648  (isNamedArg && Size <= getNativeVectorSizeForAVXABI(AVXLevel))) {
2649  // Arguments of 256-bits are split into four eightbyte chunks. The
2650  // least significant one belongs to class SSE and all the others to class
2651  // SSEUP. The original Lo and Hi design considers that types can't be
2652  // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
2653  // This design isn't correct for 256-bits, but since there're no cases
2654  // where the upper parts would need to be inspected, avoid adding
2655  // complexity and just consider Hi to match the 64-256 part.
2656  //
2657  // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
2658  // registers if they are "named", i.e. not part of the "..." of a
2659  // variadic function.
2660  //
2661  // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
2662  // split into eight eightbyte chunks, one SSE and seven SSEUP.
2663  Lo = SSE;
2664  Hi = SSEUp;
2665  }
2666  return;
2667  }
2668 
2669  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
2670  QualType ET = getContext().getCanonicalType(CT->getElementType());
2671 
2672  uint64_t Size = getContext().getTypeSize(Ty);
2673  if (ET->isIntegralOrEnumerationType()) {
2674  if (Size <= 64)
2675  Current = Integer;
2676  else if (Size <= 128)
2677  Lo = Hi = Integer;
2678  } else if (ET == getContext().FloatTy) {
2679  Current = SSE;
2680  } else if (ET == getContext().DoubleTy) {
2681  Lo = Hi = SSE;
2682  } else if (ET == getContext().LongDoubleTy) {
2683  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
2684  if (LDF == &llvm::APFloat::IEEEquad())
2685  Current = Memory;
2686  else if (LDF == &llvm::APFloat::x87DoubleExtended())
2687  Current = ComplexX87;
2688  else if (LDF == &llvm::APFloat::IEEEdouble())
2689  Lo = Hi = SSE;
2690  else
2691  llvm_unreachable("unexpected long double representation!");
2692  }
2693 
2694  // If this complex type crosses an eightbyte boundary then it
2695  // should be split.
2696  uint64_t EB_Real = (OffsetBase) / 64;
2697  uint64_t EB_Imag = (OffsetBase + getContext().getTypeSize(ET)) / 64;
2698  if (Hi == NoClass && EB_Real != EB_Imag)
2699  Hi = Lo;
2700 
2701  return;
2702  }
2703 
2704  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
2705  // Arrays are treated like structures.
2706 
2707  uint64_t Size = getContext().getTypeSize(Ty);
2708 
2709  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2710  // than eight eightbytes, ..., it has class MEMORY.
2711  if (Size > 512)
2712  return;
2713 
2714  // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2715  // fields, it has class MEMORY.
2716  //
2717  // Only need to check alignment of array base.
2718  if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2719  return;
2720 
2721  // Otherwise implement simplified merge. We could be smarter about
2722  // this, but it isn't worth it and would be harder to verify.
2723  Current = NoClass;
2724  uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2725  uint64_t ArraySize = AT->getSize().getZExtValue();
2726 
2727  // The only case a 256-bit wide vector could be used is when the array
2728  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2729  // to work for sizes wider than 128, early check and fallback to memory.
2730  //
2731  if (Size > 128 &&
2732  (Size != EltSize || Size > getNativeVectorSizeForAVXABI(AVXLevel)))
2733  return;
2734 
2735  for (uint64_t i=0, Offset=OffsetBase; i<ArraySize; ++i, Offset += EltSize) {
2736  Class FieldLo, FieldHi;
2737  classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2738  Lo = merge(Lo, FieldLo);
2739  Hi = merge(Hi, FieldHi);
2740  if (Lo == Memory || Hi == Memory)
2741  break;
2742  }
2743 
2744  postMerge(Size, Lo, Hi);
2745  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2746  return;
2747  }
2748 
2749  if (const RecordType *RT = Ty->getAs<RecordType>()) {
2750  uint64_t Size = getContext().getTypeSize(Ty);
2751 
2752  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2753  // than eight eightbytes, ..., it has class MEMORY.
2754  if (Size > 512)
2755  return;
2756 
2757  // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2758  // copy constructor or a non-trivial destructor, it is passed by invisible
2759  // reference.
2760  if (getRecordArgABI(RT, getCXXABI()))
2761  return;
2762 
2763  const RecordDecl *RD = RT->getDecl();
2764 
2765  // Assume variable sized types are passed in memory.
2766  if (RD->hasFlexibleArrayMember())
2767  return;
2768 
2769  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
2770 
2771  // Reset Lo class, this will be recomputed.
2772  Current = NoClass;
2773 
2774  // If this is a C++ record, classify the bases first.
2775  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
2776  for (const auto &I : CXXRD->bases()) {
2777  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2778  "Unexpected base class!");
2779  const CXXRecordDecl *Base =
2780  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
2781 
2782  // Classify this field.
2783  //
2784  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2785  // single eightbyte, each is classified separately. Each eightbyte gets
2786  // initialized to class NO_CLASS.
2787  Class FieldLo, FieldHi;
2788  uint64_t Offset =
2789  OffsetBase + getContext().toBits(Layout.getBaseClassOffset(Base));
2790  classify(I.getType(), Offset, FieldLo, FieldHi, isNamedArg);
2791  Lo = merge(Lo, FieldLo);
2792  Hi = merge(Hi, FieldHi);
2793  if (Lo == Memory || Hi == Memory) {
2794  postMerge(Size, Lo, Hi);
2795  return;
2796  }
2797  }
2798  }
2799 
2800  // Classify the fields one at a time, merging the results.
2801  unsigned idx = 0;
2802  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2803  i != e; ++i, ++idx) {
2804  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2805  bool BitField = i->isBitField();
2806 
2807  // Ignore padding bit-fields.
2808  if (BitField && i->isUnnamedBitfield())
2809  continue;
2810 
2811  // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2812  // four eightbytes, or it contains unaligned fields, it has class MEMORY.
2813  //
2814  // The only case a 256-bit wide vector could be used is when the struct
2815  // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2816  // to work for sizes wider than 128, early check and fallback to memory.
2817  //
2818  if (Size > 128 && (Size != getContext().getTypeSize(i->getType()) ||
2819  Size > getNativeVectorSizeForAVXABI(AVXLevel))) {
2820  Lo = Memory;
2821  postMerge(Size, Lo, Hi);
2822  return;
2823  }
2824  // Note, skip this test for bit-fields, see below.
2825  if (!BitField && Offset % getContext().getTypeAlign(i->getType())) {
2826  Lo = Memory;
2827  postMerge(Size, Lo, Hi);
2828  return;
2829  }
2830 
2831  // Classify this field.
2832  //
2833  // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2834  // exceeds a single eightbyte, each is classified
2835  // separately. Each eightbyte gets initialized to class
2836  // NO_CLASS.
2837  Class FieldLo, FieldHi;
2838 
2839  // Bit-fields require special handling, they do not force the
2840  // structure to be passed in memory even if unaligned, and
2841  // therefore they can straddle an eightbyte.
2842  if (BitField) {
2843  assert(!i->isUnnamedBitfield());
2844  uint64_t Offset = OffsetBase + Layout.getFieldOffset(idx);
2845  uint64_t Size = i->getBitWidthValue(getContext());
2846 
2847  uint64_t EB_Lo = Offset / 64;
2848  uint64_t EB_Hi = (Offset + Size - 1) / 64;
2849 
2850  if (EB_Lo) {
2851  assert(EB_Hi == EB_Lo && "Invalid classification, type > 16 bytes.");
2852  FieldLo = NoClass;
2853  FieldHi = Integer;
2854  } else {
2855  FieldLo = Integer;
2856  FieldHi = EB_Hi ? Integer : NoClass;
2857  }
2858  } else
2859  classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2860  Lo = merge(Lo, FieldLo);
2861  Hi = merge(Hi, FieldHi);
2862  if (Lo == Memory || Hi == Memory)
2863  break;
2864  }
2865 
2866  postMerge(Size, Lo, Hi);
2867  }
2868 }
2869 
2870 ABIArgInfo X86_64ABIInfo::getIndirectReturnResult(QualType Ty) const {
2871  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2872  // place naturally.
2873  if (!isAggregateTypeForABI(Ty)) {
2874  // Treat an enum type as its underlying type.
2875  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2876  Ty = EnumTy->getDecl()->getIntegerType();
2877 
2879  : ABIArgInfo::getDirect());
2880  }
2881 
2882  return getNaturalAlignIndirect(Ty);
2883 }
2884 
2885 bool X86_64ABIInfo::IsIllegalVectorType(QualType Ty) const {
2886  if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2887  uint64_t Size = getContext().getTypeSize(VecTy);
2888  unsigned LargestVector = getNativeVectorSizeForAVXABI(AVXLevel);
2889  if (Size <= 64 || Size > LargestVector)
2890  return true;
2891  }
2892 
2893  return false;
2894 }
2895 
2896 ABIArgInfo X86_64ABIInfo::getIndirectResult(QualType Ty,
2897  unsigned freeIntRegs) const {
2898  // If this is a scalar LLVM value then assume LLVM will pass it in the right
2899  // place naturally.
2900  //
2901  // This assumption is optimistic, as there could be free registers available
2902  // when we need to pass this argument in memory, and LLVM could try to pass
2903  // the argument in the free register. This does not seem to happen currently,
2904  // but this code would be much safer if we could mark the argument with
2905  // 'onstack'. See PR12193.
2906  if (!isAggregateTypeForABI(Ty) && !IsIllegalVectorType(Ty)) {
2907  // Treat an enum type as its underlying type.
2908  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2909  Ty = EnumTy->getDecl()->getIntegerType();
2910 
2912  : ABIArgInfo::getDirect());
2913  }
2914 
2917 
2918  // Compute the byval alignment. We specify the alignment of the byval in all
2919  // cases so that the mid-level optimizer knows the alignment of the byval.
2920  unsigned Align = std::max(getContext().getTypeAlign(Ty) / 8, 8U);
2921 
2922  // Attempt to avoid passing indirect results using byval when possible. This
2923  // is important for good codegen.
2924  //
2925  // We do this by coercing the value into a scalar type which the backend can
2926  // handle naturally (i.e., without using byval).
2927  //
2928  // For simplicity, we currently only do this when we have exhausted all of the
2929  // free integer registers. Doing this when there are free integer registers
2930  // would require more care, as we would have to ensure that the coerced value
2931  // did not claim the unused register. That would require either reording the
2932  // arguments to the function (so that any subsequent inreg values came first),
2933  // or only doing this optimization when there were no following arguments that
2934  // might be inreg.
2935  //
2936  // We currently expect it to be rare (particularly in well written code) for
2937  // arguments to be passed on the stack when there are still free integer
2938  // registers available (this would typically imply large structs being passed
2939  // by value), so this seems like a fair tradeoff for now.
2940  //
2941  // We can revisit this if the backend grows support for 'onstack' parameter
2942  // attributes. See PR12193.
2943  if (freeIntRegs == 0) {
2944  uint64_t Size = getContext().getTypeSize(Ty);
2945 
2946  // If this type fits in an eightbyte, coerce it into the matching integral
2947  // type, which will end up on the stack (with alignment 8).
2948  if (Align == 8 && Size <= 64)
2949  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),
2950  Size));
2951  }
2952 
2954 }
2955 
2956 /// The ABI specifies that a value should be passed in a full vector XMM/YMM
2957 /// register. Pick an LLVM IR type that will be passed as a vector register.
2958 llvm::Type *X86_64ABIInfo::GetByteVectorType(QualType Ty) const {
2959  // Wrapper structs/arrays that only contain vectors are passed just like
2960  // vectors; strip them off if present.
2961  if (const Type *InnerTy = isSingleElementStruct(Ty, getContext()))
2962  Ty = QualType(InnerTy, 0);
2963 
2964  llvm::Type *IRType = CGT.ConvertType(Ty);
2965  if (isa<llvm::VectorType>(IRType) ||
2966  IRType->getTypeID() == llvm::Type::FP128TyID)
2967  return IRType;
2968 
2969  // We couldn't find the preferred IR vector type for 'Ty'.
2970  uint64_t Size = getContext().getTypeSize(Ty);
2971  assert((Size == 128 || Size == 256 || Size == 512) && "Invalid type found!");
2972 
2973  // Return a LLVM IR vector type based on the size of 'Ty'.
2974  return llvm::VectorType::get(llvm::Type::getDoubleTy(getVMContext()),
2975  Size / 64);
2976 }
2977 
2978 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2979 /// is known to either be off the end of the specified type or being in
2980 /// alignment padding. The user type specified is known to be at most 128 bits
2981 /// in size, and have passed through X86_64ABIInfo::classify with a successful
2982 /// classification that put one of the two halves in the INTEGER class.
2983 ///
2984 /// It is conservatively correct to return false.
2985 static bool BitsContainNoUserData(QualType Ty, unsigned StartBit,
2986  unsigned EndBit, ASTContext &Context) {
2987  // If the bytes being queried are off the end of the type, there is no user
2988  // data hiding here. This handles analysis of builtins, vectors and other
2989  // types that don't contain interesting padding.
2990  unsigned TySize = (unsigned)Context.getTypeSize(Ty);
2991  if (TySize <= StartBit)
2992  return true;
2993 
2994  if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) {
2995  unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2996  unsigned NumElts = (unsigned)AT->getSize().getZExtValue();
2997 
2998  // Check each element to see if the element overlaps with the queried range.
2999  for (unsigned i = 0; i != NumElts; ++i) {
3000  // If the element is after the span we care about, then we're done..
3001  unsigned EltOffset = i*EltSize;
3002  if (EltOffset >= EndBit) break;
3003 
3004  unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
3005  if (!BitsContainNoUserData(AT->getElementType(), EltStart,
3006  EndBit-EltOffset, Context))
3007  return false;
3008  }
3009  // If it overlaps no elements, then it is safe to process as padding.
3010  return true;
3011  }
3012 
3013  if (const RecordType *RT = Ty->getAs<RecordType>()) {
3014  const RecordDecl *RD = RT->getDecl();
3015  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
3016 
3017  // If this is a C++ record, check the bases first.
3018  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
3019  for (const auto &I : CXXRD->bases()) {
3020  assert(!I.isVirtual() && !I.getType()->isDependentType() &&
3021  "Unexpected base class!");
3022  const CXXRecordDecl *Base =
3023  cast<CXXRecordDecl>(I.getType()->getAs<RecordType>()->getDecl());
3024 
3025  // If the base is after the span we care about, ignore it.
3026  unsigned BaseOffset = Context.toBits(Layout.getBaseClassOffset(Base));
3027  if (BaseOffset >= EndBit) continue;
3028 
3029  unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
3030  if (!BitsContainNoUserData(I.getType(), BaseStart,
3031  EndBit-BaseOffset, Context))
3032  return false;
3033  }
3034  }
3035 
3036  // Verify that no field has data that overlaps the region of interest. Yes
3037  // this could be sped up a lot by being smarter about queried fields,
3038  // however we're only looking at structs up to 16 bytes, so we don't care
3039  // much.
3040  unsigned idx = 0;
3041  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
3042  i != e; ++i, ++idx) {
3043  unsigned FieldOffset = (unsigned)Layout.getFieldOffset(idx);
3044 
3045  // If we found a field after the region we care about, then we're done.
3046  if (FieldOffset >= EndBit) break;
3047 
3048  unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
3049  if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
3050  Context))
3051  return false;
3052  }
3053 
3054  // If nothing in this record overlapped the area of interest, then we're
3055  // clean.
3056  return true;
3057  }
3058 
3059  return false;
3060 }
3061 
3062 /// ContainsFloatAtOffset - Return true if the specified LLVM IR type has a
3063 /// float member at the specified offset. For example, {int,{float}} has a
3064 /// float at offset 4. It is conservatively correct for this routine to return
3065 /// false.
3066 static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset,
3067  const llvm::DataLayout &TD) {
3068  // Base case if we find a float.
3069  if (IROffset == 0 && IRType->isFloatTy())
3070  return true;
3071 
3072  // If this is a struct, recurse into the field at the specified offset.
3073  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3074  const llvm::StructLayout *SL = TD.getStructLayout(STy);
3075  unsigned Elt = SL->getElementContainingOffset(IROffset);
3076  IROffset -= SL->getElementOffset(Elt);
3077  return ContainsFloatAtOffset(STy->getElementType(Elt), IROffset, TD);
3078  }
3079 
3080  // If this is an array, recurse into the field at the specified offset.
3081  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3082  llvm::Type *EltTy = ATy->getElementType();
3083  unsigned EltSize = TD.getTypeAllocSize(EltTy);
3084  IROffset -= IROffset/EltSize*EltSize;
3085  return ContainsFloatAtOffset(EltTy, IROffset, TD);
3086  }
3087 
3088  return false;
3089 }
3090 
3091 
3092 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
3093 /// low 8 bytes of an XMM register, corresponding to the SSE class.
3094 llvm::Type *X86_64ABIInfo::
3095 GetSSETypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3096  QualType SourceTy, unsigned SourceOffset) const {
3097  // The only three choices we have are either double, <2 x float>, or float. We
3098  // pass as float if the last 4 bytes is just padding. This happens for
3099  // structs that contain 3 floats.
3100  if (BitsContainNoUserData(SourceTy, SourceOffset*8+32,
3101  SourceOffset*8+64, getContext()))
3102  return llvm::Type::getFloatTy(getVMContext());
3103 
3104  // We want to pass as <2 x float> if the LLVM IR type contains a float at
3105  // offset+0 and offset+4. Walk the LLVM IR type to find out if this is the
3106  // case.
3107  if (ContainsFloatAtOffset(IRType, IROffset, getDataLayout()) &&
3108  ContainsFloatAtOffset(IRType, IROffset+4, getDataLayout()))
3109  return llvm::VectorType::get(llvm::Type::getFloatTy(getVMContext()), 2);
3110 
3111  return llvm::Type::getDoubleTy(getVMContext());
3112 }
3113 
3114 
3115 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
3116 /// an 8-byte GPR. This means that we either have a scalar or we are talking
3117 /// about the high or low part of an up-to-16-byte struct. This routine picks
3118 /// the best LLVM IR type to represent this, which may be i64 or may be anything
3119 /// else that the backend will pass in a GPR that works better (e.g. i8, %foo*,
3120 /// etc).
3121 ///
3122 /// PrefType is an LLVM IR type that corresponds to (part of) the IR type for
3123 /// the source type. IROffset is an offset in bytes into the LLVM IR type that
3124 /// the 8-byte value references. PrefType may be null.
3125 ///
3126 /// SourceTy is the source-level type for the entire argument. SourceOffset is
3127 /// an offset into this that we're processing (which is always either 0 or 8).
3128 ///
3129 llvm::Type *X86_64ABIInfo::
3130 GetINTEGERTypeAtOffset(llvm::Type *IRType, unsigned IROffset,
3131  QualType SourceTy, unsigned SourceOffset) const {
3132  // If we're dealing with an un-offset LLVM IR type, then it means that we're
3133  // returning an 8-byte unit starting with it. See if we can safely use it.
3134  if (IROffset == 0) {
3135  // Pointers and int64's always fill the 8-byte unit.
3136  if ((isa<llvm::PointerType>(IRType) && Has64BitPointers) ||
3137  IRType->isIntegerTy(64))
3138  return IRType;
3139 
3140  // If we have a 1/2/4-byte integer, we can use it only if the rest of the
3141  // goodness in the source type is just tail padding. This is allowed to
3142  // kick in for struct {double,int} on the int, but not on
3143  // struct{double,int,int} because we wouldn't return the second int. We
3144  // have to do this analysis on the source type because we can't depend on
3145  // unions being lowered a specific way etc.
3146  if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
3147  IRType->isIntegerTy(32) ||
3148  (isa<llvm::PointerType>(IRType) && !Has64BitPointers)) {
3149  unsigned BitWidth = isa<llvm::PointerType>(IRType) ? 32 :
3150  cast<llvm::IntegerType>(IRType)->getBitWidth();
3151 
3152  if (BitsContainNoUserData(SourceTy, SourceOffset*8+BitWidth,
3153  SourceOffset*8+64, getContext()))
3154  return IRType;
3155  }
3156  }
3157 
3158  if (llvm::StructType *STy = dyn_cast<llvm::StructType>(IRType)) {
3159  // If this is a struct, recurse into the field at the specified offset.
3160  const llvm::StructLayout *SL = getDataLayout().getStructLayout(STy);
3161  if (IROffset < SL->getSizeInBytes()) {
3162  unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
3163  IROffset -= SL->getElementOffset(FieldIdx);
3164 
3165  return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
3166  SourceTy, SourceOffset);
3167  }
3168  }
3169 
3170  if (llvm::ArrayType *ATy = dyn_cast<llvm::ArrayType>(IRType)) {
3171  llvm::Type *EltTy = ATy->getElementType();
3172  unsigned EltSize = getDataLayout().getTypeAllocSize(EltTy);
3173  unsigned EltOffset = IROffset/EltSize*EltSize;
3174  return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
3175  SourceOffset);
3176  }
3177 
3178  // Okay, we don't have any better idea of what to pass, so we pass this in an
3179  // integer register that isn't too big to fit the rest of the struct.
3180  unsigned TySizeInBytes =
3181  (unsigned)getContext().getTypeSizeInChars(SourceTy).getQuantity();
3182 
3183  assert(TySizeInBytes != SourceOffset && "Empty field?");
3184 
3185  // It is always safe to classify this as an integer type up to i64 that
3186  // isn't larger than the structure.
3187  return llvm::IntegerType::get(getVMContext(),
3188  std::min(TySizeInBytes-SourceOffset, 8U)*8);
3189 }
3190 
3191 
3192 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
3193 /// be used as elements of a two register pair to pass or return, return a
3194 /// first class aggregate to represent them. For example, if the low part of
3195 /// a by-value argument should be passed as i32* and the high part as float,
3196 /// return {i32*, float}.
3197 static llvm::Type *
3199  const llvm::DataLayout &TD) {
3200  // In order to correctly satisfy the ABI, we need to the high part to start
3201  // at offset 8. If the high and low parts we inferred are both 4-byte types
3202  // (e.g. i32 and i32) then the resultant struct type ({i32,i32}) won't have
3203  // the second element at offset 8. Check for this:
3204  unsigned LoSize = (unsigned)TD.getTypeAllocSize(Lo);
3205  unsigned HiAlign = TD.getABITypeAlignment(Hi);
3206  unsigned HiStart = llvm::alignTo(LoSize, HiAlign);
3207  assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
3208 
3209  // To handle this, we have to increase the size of the low part so that the
3210  // second element will start at an 8 byte offset. We can't increase the size
3211  // of the second element because it might make us access off the end of the
3212  // struct.
3213  if (HiStart != 8) {
3214  // There are usually two sorts of types the ABI generation code can produce
3215  // for the low part of a pair that aren't 8 bytes in size: float or
3216  // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
3217  // NaCl).
3218  // Promote these to a larger type.
3219  if (Lo->isFloatTy())
3220  Lo = llvm::Type::getDoubleTy(Lo->getContext());
3221  else {
3222  assert((Lo->isIntegerTy() || Lo->isPointerTy())
3223  && "Invalid/unknown lo type");
3224  Lo = llvm::Type::getInt64Ty(Lo->getContext());
3225  }
3226  }
3227 
3228  llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
3229 
3230  // Verify that the second element is at an 8-byte offset.
3231  assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
3232  "Invalid x86-64 argument pair!");
3233  return Result;
3234 }
3235 
3237 classifyReturnType(QualType RetTy) const {
3238  // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
3239  // classification algorithm.
3240  X86_64ABIInfo::Class Lo, Hi;
3241  classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
3242 
3243  // Check some invariants.
3244  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3245  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3246 
3247  llvm::Type *ResType = nullptr;
3248  switch (Lo) {
3249  case NoClass:
3250  if (Hi == NoClass)
3251  return ABIArgInfo::getIgnore();
3252  // If the low part is just padding, it takes no register, leave ResType
3253  // null.
3254  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3255  "Unknown missing lo part");
3256  break;
3257 
3258  case SSEUp:
3259  case X87Up:
3260  llvm_unreachable("Invalid classification for lo word.");
3261 
3262  // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
3263  // hidden argument.
3264  case Memory:
3265  return getIndirectReturnResult(RetTy);
3266 
3267  // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
3268  // available register of the sequence %rax, %rdx is used.
3269  case Integer:
3270  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3271 
3272  // If we have a sign or zero extended integer, make sure to return Extend
3273  // so that the parameter gets the right LLVM IR attributes.
3274  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3275  // Treat an enum type as its underlying type.
3276  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
3277  RetTy = EnumTy->getDecl()->getIntegerType();
3278 
3279  if (RetTy->isIntegralOrEnumerationType() &&
3280  RetTy->isPromotableIntegerType())
3281  return ABIArgInfo::getExtend(RetTy);
3282  }
3283  break;
3284 
3285  // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
3286  // available SSE register of the sequence %xmm0, %xmm1 is used.
3287  case SSE:
3288  ResType = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 0, RetTy, 0);
3289  break;
3290 
3291  // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
3292  // returned on the X87 stack in %st0 as 80-bit x87 number.
3293  case X87:
3294  ResType = llvm::Type::getX86_FP80Ty(getVMContext());
3295  break;
3296 
3297  // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
3298  // part of the value is returned in %st0 and the imaginary part in
3299  // %st1.
3300  case ComplexX87:
3301  assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
3302  ResType = llvm::StructType::get(llvm::Type::getX86_FP80Ty(getVMContext()),
3303  llvm::Type::getX86_FP80Ty(getVMContext()));
3304  break;
3305  }
3306 
3307  llvm::Type *HighPart = nullptr;
3308  switch (Hi) {
3309  // Memory was handled previously and X87 should
3310  // never occur as a hi class.
3311  case Memory:
3312  case X87:
3313  llvm_unreachable("Invalid classification for hi word.");
3314 
3315  case ComplexX87: // Previously handled.
3316  case NoClass:
3317  break;
3318 
3319  case Integer:
3320  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3321  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3322  return ABIArgInfo::getDirect(HighPart, 8);
3323  break;
3324  case SSE:
3325  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3326  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3327  return ABIArgInfo::getDirect(HighPart, 8);
3328  break;
3329 
3330  // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
3331  // is passed in the next available eightbyte chunk if the last used
3332  // vector register.
3333  //
3334  // SSEUP should always be preceded by SSE, just widen.
3335  case SSEUp:
3336  assert(Lo == SSE && "Unexpected SSEUp classification.");
3337  ResType = GetByteVectorType(RetTy);
3338  break;
3339 
3340  // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
3341  // returned together with the previous X87 value in %st0.
3342  case X87Up:
3343  // If X87Up is preceded by X87, we don't need to do
3344  // anything. However, in some cases with unions it may not be
3345  // preceded by X87. In such situations we follow gcc and pass the
3346  // extra bits in an SSE reg.
3347  if (Lo != X87) {
3348  HighPart = GetSSETypeAtOffset(CGT.ConvertType(RetTy), 8, RetTy, 8);
3349  if (Lo == NoClass) // Return HighPart at offset 8 in memory.
3350  return ABIArgInfo::getDirect(HighPart, 8);
3351  }
3352  break;
3353  }
3354 
3355  // If a high part was specified, merge it together with the low part. It is
3356  // known to pass in the high eightbyte of the result. We do this by forming a
3357  // first class struct aggregate with the high and low part: {low, high}
3358  if (HighPart)
3359  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3360 
3361  return ABIArgInfo::getDirect(ResType);
3362 }
3363 
3365  QualType Ty, unsigned freeIntRegs, unsigned &neededInt, unsigned &neededSSE,
3366  bool isNamedArg)
3367  const
3368 {
3370 
3371  X86_64ABIInfo::Class Lo, Hi;
3372  classify(Ty, 0, Lo, Hi, isNamedArg);
3373 
3374  // Check some invariants.
3375  // FIXME: Enforce these by construction.
3376  assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
3377  assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
3378 
3379  neededInt = 0;
3380  neededSSE = 0;
3381  llvm::Type *ResType = nullptr;
3382  switch (Lo) {
3383  case NoClass:
3384  if (Hi == NoClass)
3385  return ABIArgInfo::getIgnore();
3386  // If the low part is just padding, it takes no register, leave ResType
3387  // null.
3388  assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
3389  "Unknown missing lo part");
3390  break;
3391 
3392  // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
3393  // on the stack.
3394  case Memory:
3395 
3396  // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
3397  // COMPLEX_X87, it is passed in memory.
3398  case X87:
3399  case ComplexX87:
3401  ++neededInt;
3402  return getIndirectResult(Ty, freeIntRegs);
3403 
3404  case SSEUp:
3405  case X87Up:
3406  llvm_unreachable("Invalid classification for lo word.");
3407 
3408  // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
3409  // available register of the sequence %rdi, %rsi, %rdx, %rcx, %r8
3410  // and %r9 is used.
3411  case Integer:
3412  ++neededInt;
3413 
3414  // Pick an 8-byte type based on the preferred type.
3415  ResType = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 0, Ty, 0);
3416 
3417  // If we have a sign or zero extended integer, make sure to return Extend
3418  // so that the parameter gets the right LLVM IR attributes.
3419  if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
3420  // Treat an enum type as its underlying type.
3421  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3422  Ty = EnumTy->getDecl()->getIntegerType();
3423 
3424  if (Ty->isIntegralOrEnumerationType() &&
3426  return ABIArgInfo::getExtend(Ty);
3427  }
3428 
3429  break;
3430 
3431  // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
3432  // available SSE register is used, the registers are taken in the
3433  // order from %xmm0 to %xmm7.
3434  case SSE: {
3435  llvm::Type *IRType = CGT.ConvertType(Ty);
3436  ResType = GetSSETypeAtOffset(IRType, 0, Ty, 0);
3437  ++neededSSE;
3438  break;
3439  }
3440  }
3441 
3442  llvm::Type *HighPart = nullptr;
3443  switch (Hi) {
3444  // Memory was handled previously, ComplexX87 and X87 should
3445  // never occur as hi classes, and X87Up must be preceded by X87,
3446  // which is passed in memory.
3447  case Memory:
3448  case X87:
3449  case ComplexX87:
3450  llvm_unreachable("Invalid classification for hi word.");
3451 
3452  case NoClass: break;
3453 
3454  case Integer:
3455  ++neededInt;
3456  // Pick an 8-byte type based on the preferred type.
3457  HighPart = GetINTEGERTypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3458 
3459  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3460  return ABIArgInfo::getDirect(HighPart, 8);
3461  break;
3462 
3463  // X87Up generally doesn't occur here (long double is passed in
3464  // memory), except in situations involving unions.
3465  case X87Up:
3466  case SSE:
3467  HighPart = GetSSETypeAtOffset(CGT.ConvertType(Ty), 8, Ty, 8);
3468 
3469  if (Lo == NoClass) // Pass HighPart at offset 8 in memory.
3470  return ABIArgInfo::getDirect(HighPart, 8);
3471 
3472  ++neededSSE;
3473  break;
3474 
3475  // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
3476  // eightbyte is passed in the upper half of the last used SSE
3477  // register. This only happens when 128-bit vectors are passed.
3478  case SSEUp:
3479  assert(Lo == SSE && "Unexpected SSEUp classification");
3480  ResType = GetByteVectorType(Ty);
3481  break;
3482  }
3483 
3484  // If a high part was specified, merge it together with the low part. It is
3485  // known to pass in the high eightbyte of the result. We do this by forming a
3486  // first class struct aggregate with the high and low part: {low, high}
3487  if (HighPart)
3488  ResType = GetX86_64ByValArgumentPair(ResType, HighPart, getDataLayout());
3489 
3490  return ABIArgInfo::getDirect(ResType);
3491 }
3492 
3493 ABIArgInfo
3494 X86_64ABIInfo::classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt,
3495  unsigned &NeededSSE) const {
3496  auto RT = Ty->getAs<RecordType>();
3497  assert(RT && "classifyRegCallStructType only valid with struct types");
3498 
3499  if (RT->getDecl()->hasFlexibleArrayMember())
3500  return getIndirectReturnResult(Ty);
3501 
3502  // Sum up bases
3503  if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
3504  if (CXXRD->isDynamicClass()) {
3505  NeededInt = NeededSSE = 0;
3506  return getIndirectReturnResult(Ty);
3507  }
3508 
3509  for (const auto &I : CXXRD->bases())
3510  if (classifyRegCallStructTypeImpl(I.getType(), NeededInt, NeededSSE)
3511  .isIndirect()) {
3512  NeededInt = NeededSSE = 0;
3513  return getIndirectReturnResult(Ty);
3514  }
3515  }
3516 
3517  // Sum up members
3518  for (const auto *FD : RT->getDecl()->fields()) {
3519  if (FD->getType()->isRecordType() && !FD->getType()->isUnionType()) {
3520  if (classifyRegCallStructTypeImpl(FD->getType(), NeededInt, NeededSSE)
3521  .isIndirect()) {
3522  NeededInt = NeededSSE = 0;
3523  return getIndirectReturnResult(Ty);
3524  }
3525  } else {
3526  unsigned LocalNeededInt, LocalNeededSSE;
3527  if (classifyArgumentType(FD->getType(), UINT_MAX, LocalNeededInt,
3528  LocalNeededSSE, true)
3529  .isIndirect()) {
3530  NeededInt = NeededSSE = 0;
3531  return getIndirectReturnResult(Ty);
3532  }
3533  NeededInt += LocalNeededInt;
3534  NeededSSE += LocalNeededSSE;
3535  }
3536  }
3537 
3538  return ABIArgInfo::getDirect();
3539 }
3540 
3541 ABIArgInfo X86_64ABIInfo::classifyRegCallStructType(QualType Ty,
3542  unsigned &NeededInt,
3543  unsigned &NeededSSE) const {
3544 
3545  NeededInt = 0;
3546  NeededSSE = 0;
3547 
3548  return classifyRegCallStructTypeImpl(Ty, NeededInt, NeededSSE);
3549 }
3550 
3551 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3552 
3553  const unsigned CallingConv = FI.getCallingConvention();
3554  // It is possible to force Win64 calling convention on any x86_64 target by
3555  // using __attribute__((ms_abi)). In such case to correctly emit Win64
3556  // compatible code delegate this call to WinX86_64ABIInfo::computeInfo.
3557  if (CallingConv == llvm::CallingConv::Win64) {
3558  WinX86_64ABIInfo Win64ABIInfo(CGT);
3559  Win64ABIInfo.computeInfo(FI);
3560  return;
3561  }
3562 
3563  bool IsRegCall = CallingConv == llvm::CallingConv::X86_RegCall;
3564 
3565  // Keep track of the number of assigned registers.
3566  unsigned FreeIntRegs = IsRegCall ? 11 : 6;
3567  unsigned FreeSSERegs = IsRegCall ? 16 : 8;
3568  unsigned NeededInt, NeededSSE;
3569 
3570  if (!::classifyReturnType(getCXXABI(), FI, *this)) {
3571  if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
3572  !FI.getReturnType()->getTypePtr()->isUnionType()) {
3573  FI.getReturnInfo() =
3574  classifyRegCallStructType(FI.getReturnType(), NeededInt, NeededSSE);
3575  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3576  FreeIntRegs -= NeededInt;
3577  FreeSSERegs -= NeededSSE;
3578  } else {
3579  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3580  }
3581  } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>()) {
3582  // Complex Long Double Type is passed in Memory when Regcall
3583  // calling convention is used.
3584  const ComplexType *CT = FI.getReturnType()->getAs<ComplexType>();
3587  FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
3588  } else
3590  }
3591 
3592  // If the return value is indirect, then the hidden argument is consuming one
3593  // integer register.
3594  if (FI.getReturnInfo().isIndirect())
3595  --FreeIntRegs;
3596 
3597  // The chain argument effectively gives us another free register.
3598  if (FI.isChainCall())
3599  ++FreeIntRegs;
3600 
3601  unsigned NumRequiredArgs = FI.getNumRequiredArgs();
3602  // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
3603  // get assigned (in left-to-right order) for passing as follows...
3604  unsigned ArgNo = 0;
3605  for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
3606  it != ie; ++it, ++ArgNo) {
3607  bool IsNamedArg = ArgNo < NumRequiredArgs;
3608 
3609  if (IsRegCall && it->type->isStructureOrClassType())
3610  it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE);
3611  else
3612  it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
3613  NeededSSE, IsNamedArg);
3614 
3615  // AMD64-ABI 3.2.3p3: If there are no registers available for any
3616  // eightbyte of an argument, the whole argument is passed on the
3617  // stack. If registers have already been assigned for some
3618  // eightbytes of such an argument, the assignments get reverted.
3619  if (FreeIntRegs >= NeededInt && FreeSSERegs >= NeededSSE) {
3620  FreeIntRegs -= NeededInt;
3621  FreeSSERegs -= NeededSSE;
3622  } else {
3623  it->info = getIndirectResult(it->type, FreeIntRegs);
3624  }
3625  }
3626 }
3627 
3629  Address VAListAddr, QualType Ty) {
3630  Address overflow_arg_area_p = CGF.Builder.CreateStructGEP(
3631  VAListAddr, 2, CharUnits::fromQuantity(8), "overflow_arg_area_p");
3632  llvm::Value *overflow_arg_area =
3633  CGF.Builder.CreateLoad(overflow_arg_area_p, "overflow_arg_area");
3634 
3635  // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3636  // byte boundary if alignment needed by type exceeds 8 byte boundary.
3637  // It isn't stated explicitly in the standard, but in practice we use
3638  // alignment greater than 16 where necessary.
3639  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
3640  if (Align > CharUnits::fromQuantity(8)) {
3641  overflow_arg_area = emitRoundPointerUpToAlignment(CGF, overflow_arg_area,
3642  Align);
3643  }
3644 
3645  // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3646  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3647  llvm::Value *Res =
3648  CGF.Builder.CreateBitCast(overflow_arg_area,
3649  llvm::PointerType::getUnqual(LTy));
3650 
3651  // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3652  // l->overflow_arg_area + sizeof(type).
3653  // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3654  // an 8 byte boundary.
3655 
3656  uint64_t SizeInBytes = (CGF.getContext().getTypeSize(Ty) + 7) / 8;
3657  llvm::Value *Offset =
3658  llvm::ConstantInt::get(CGF.Int32Ty, (SizeInBytes + 7) & ~7);
3659  overflow_arg_area = CGF.Builder.CreateGEP(overflow_arg_area, Offset,
3660  "overflow_arg_area.next");
3661  CGF.Builder.CreateStore(overflow_arg_area, overflow_arg_area_p);
3662 
3663  // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3664  return Address(Res, Align);
3665 }
3666 
3667 Address X86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
3668  QualType Ty) const {
3669  // Assume that va_list type is correct; should be pointer to LLVM type:
3670  // struct {
3671  // i32 gp_offset;
3672  // i32 fp_offset;
3673  // i8* overflow_arg_area;
3674  // i8* reg_save_area;
3675  // };
3676  unsigned neededInt, neededSSE;
3677 
3678  Ty = getContext().getCanonicalType(Ty);
3679  ABIArgInfo AI = classifyArgumentType(Ty, 0, neededInt, neededSSE,
3680  /*isNamedArg*/false);
3681 
3682  // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3683  // in the registers. If not go to step 7.
3684  if (!neededInt && !neededSSE)
3685  return EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3686 
3687  // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3688  // general purpose registers needed to pass type and num_fp to hold
3689  // the number of floating point registers needed.
3690 
3691  // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3692  // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3693  // l->fp_offset > 304 - num_fp * 16 go to step 7.
3694  //
3695  // NOTE: 304 is a typo, there are (6 * 8 + 8 * 16) = 176 bytes of
3696  // register save space).
3697 
3698  llvm::Value *InRegs = nullptr;
3699  Address gp_offset_p = Address::invalid(), fp_offset_p = Address::invalid();
3700  llvm::Value *gp_offset = nullptr, *fp_offset = nullptr;
3701  if (neededInt) {
3702  gp_offset_p =
3703  CGF.Builder.CreateStructGEP(VAListAddr, 0, CharUnits::Zero(),
3704  "gp_offset_p");
3705  gp_offset = CGF.Builder.CreateLoad(gp_offset_p, "gp_offset");
3706  InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3707  InRegs = CGF.Builder.CreateICmpULE(gp_offset, InRegs, "fits_in_gp");
3708  }
3709 
3710  if (neededSSE) {
3711  fp_offset_p =
3712  CGF.Builder.CreateStructGEP(VAListAddr, 1, CharUnits::fromQuantity(4),
3713  "fp_offset_p");
3714  fp_offset = CGF.Builder.CreateLoad(fp_offset_p, "fp_offset");
3715  llvm::Value *FitsInFP =
3716  llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3717  FitsInFP = CGF.Builder.CreateICmpULE(fp_offset, FitsInFP, "fits_in_fp");
3718  InRegs = InRegs ? CGF.Builder.CreateAnd(InRegs, FitsInFP) : FitsInFP;
3719  }
3720 
3721  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
3722  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
3723  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
3724  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
3725 
3726  // Emit code to load the value if it was passed in registers.
3727 
3728  CGF.EmitBlock(InRegBlock);
3729 
3730  // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3731  // an offset of l->gp_offset and/or l->fp_offset. This may require
3732  // copying to a temporary location in case the parameter is passed
3733  // in different register classes or requires an alignment greater
3734  // than 8 for general purpose registers and 16 for XMM registers.
3735  //
3736  // FIXME: This really results in shameful code when we end up needing to
3737  // collect arguments from different places; often what should result in a
3738  // simple assembling of a structure from scattered addresses has many more
3739  // loads than necessary. Can we clean this up?
3740  llvm::Type *LTy = CGF.ConvertTypeForMem(Ty);
3741  llvm::Value *RegSaveArea = CGF.Builder.CreateLoad(
3742  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(16)),
3743  "reg_save_area");
3744 
3745  Address RegAddr = Address::invalid();
3746  if (neededInt && neededSSE) {
3747  // FIXME: Cleanup.
3748  assert(AI.isDirect() && "Unexpected ABI info for mixed regs");
3749  llvm::StructType *ST = cast<llvm::StructType>(AI.getCoerceToType());
3750  Address Tmp = CGF.CreateMemTemp(Ty);
3751  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3752  assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3753  llvm::Type *TyLo = ST->getElementType(0);
3754  llvm::Type *TyHi = ST->getElementType(1);
3755  assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3756  "Unexpected ABI info for mixed regs");
3757  llvm::Type *PTyLo = llvm::PointerType::getUnqual(TyLo);
3758  llvm::Type *PTyHi = llvm::PointerType::getUnqual(TyHi);
3759  llvm::Value *GPAddr = CGF.Builder.CreateGEP(RegSaveArea, gp_offset);
3760  llvm::Value *FPAddr = CGF.Builder.CreateGEP(RegSaveArea, fp_offset);
3761  llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3762  llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3763 
3764  // Copy the first element.
3765  // FIXME: Our choice of alignment here and below is probably pessimistic.
3767  TyLo, CGF.Builder.CreateBitCast(RegLoAddr, PTyLo),
3768  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyLo)));
3769  CGF.Builder.CreateStore(V,
3770  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3771 
3772  // Copy the second element.
3773  V = CGF.Builder.CreateAlignedLoad(
3774  TyHi, CGF.Builder.CreateBitCast(RegHiAddr, PTyHi),
3775  CharUnits::fromQuantity(getDataLayout().getABITypeAlignment(TyHi)));
3777  getDataLayout().getStructLayout(ST)->getElementOffset(1));
3778  CGF.Builder.CreateStore(V, CGF.Builder.CreateStructGEP(Tmp, 1, Offset));
3779 
3780  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3781  } else if (neededInt) {
3782  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, gp_offset),
3784  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3785 
3786  // Copy to a temporary if necessary to ensure the appropriate alignment.
3787  std::pair<CharUnits, CharUnits> SizeAlign =
3789  uint64_t TySize = SizeAlign.first.getQuantity();
3790  CharUnits TyAlign = SizeAlign.second;
3791 
3792  // Copy into a temporary if the type is more aligned than the
3793  // register save area.
3794  if (TyAlign.getQuantity() > 8) {
3795  Address Tmp = CGF.CreateMemTemp(Ty);
3796  CGF.Builder.CreateMemCpy(Tmp, RegAddr, TySize, false);
3797  RegAddr = Tmp;
3798  }
3799 
3800  } else if (neededSSE == 1) {
3801  RegAddr = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3803  RegAddr = CGF.Builder.CreateElementBitCast(RegAddr, LTy);
3804  } else {
3805  assert(neededSSE == 2 && "Invalid number of needed registers!");
3806  // SSE registers are spaced 16 bytes apart in the register save
3807  // area, we need to collect the two eightbytes together.
3808  // The ABI isn't explicit about this, but it seems reasonable
3809  // to assume that the slots are 16-byte aligned, since the stack is
3810  // naturally 16-byte aligned and the prologue is expected to store
3811  // all the SSE registers to the RSA.
3812  Address RegAddrLo = Address(CGF.Builder.CreateGEP(RegSaveArea, fp_offset),
3814  Address RegAddrHi =
3815  CGF.Builder.CreateConstInBoundsByteGEP(RegAddrLo,
3817  llvm::Type *ST = AI.canHaveCoerceToType()
3818  ? AI.getCoerceToType()
3819  : llvm::StructType::get(CGF.DoubleTy, CGF.DoubleTy);
3820  llvm::Value *V;
3821  Address Tmp = CGF.CreateMemTemp(Ty);
3822  Tmp = CGF.Builder.CreateElementBitCast(Tmp, ST);
3824  RegAddrLo, ST->getStructElementType(0)));
3825  CGF.Builder.CreateStore(V,
3826  CGF.Builder.CreateStructGEP(Tmp, 0, CharUnits::Zero()));
3828  RegAddrHi, ST->getStructElementType(1)));
3829  CGF.Builder.CreateStore(V,
3831 
3832  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, LTy);
3833  }
3834 
3835  // AMD64-ABI 3.5.7p5: Step 5. Set:
3836  // l->gp_offset = l->gp_offset + num_gp * 8
3837  // l->fp_offset = l->fp_offset + num_fp * 16.
3838  if (neededInt) {
3839  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededInt * 8);
3840  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(gp_offset, Offset),
3841  gp_offset_p);
3842  }
3843  if (neededSSE) {
3844  llvm::Value *Offset = llvm::ConstantInt::get(CGF.Int32Ty, neededSSE * 16);
3845  CGF.Builder.CreateStore(CGF.Builder.CreateAdd(fp_offset, Offset),
3846  fp_offset_p);
3847  }
3848  CGF.EmitBranch(ContBlock);
3849 
3850  // Emit code to load the value if it was passed in memory.
3851 
3852  CGF.EmitBlock(InMemBlock);
3853  Address MemAddr = EmitX86_64VAArgFromMemory(CGF, VAListAddr, Ty);
3854 
3855  // Return the appropriate result.
3856 
3857  CGF.EmitBlock(ContBlock);
3858  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock, MemAddr, InMemBlock,
3859  "vaarg.addr");
3860  return ResAddr;
3861 }
3862 
3863 Address X86_64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
3864  QualType Ty) const {
3865  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
3866  CGF.getContext().getTypeInfoInChars(Ty),
3868  /*allowHigherAlign*/ false);
3869 }
3870 
3871 ABIArgInfo
3872 WinX86_64ABIInfo::reclassifyHvaArgType(QualType Ty, unsigned &FreeSSERegs,
3873  const ABIArgInfo &current) const {
3874  // Assumes vectorCall calling convention.
3875  const Type *Base = nullptr;
3876  uint64_t NumElts = 0;
3877 
3878  if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3879  isHomogeneousAggregate(Ty, Base, NumElts) && FreeSSERegs >= NumElts) {
3880  FreeSSERegs -= NumElts;
3881  return getDirectX86Hva();
3882  }
3883  return current;
3884 }
3885 
3886 ABIArgInfo WinX86_64ABIInfo::classify(QualType Ty, unsigned &FreeSSERegs,
3887  bool IsReturnType, bool IsVectorCall,
3888  bool IsRegCall) const {
3889 
3890  if (Ty->isVoidType())
3891  return ABIArgInfo::getIgnore();
3892 
3893  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3894  Ty = EnumTy->getDecl()->getIntegerType();
3895 
3896  TypeInfo Info = getContext().getTypeInfo(Ty);
3897  uint64_t Width = Info.Width;
3899 
3900  const RecordType *RT = Ty->getAs<RecordType>();
3901  if (RT) {
3902  if (!IsReturnType) {
3905  }
3906 
3907  if (RT->getDecl()->hasFlexibleArrayMember())
3908  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3909 
3910  }
3911 
3912  const Type *Base = nullptr;
3913  uint64_t NumElts = 0;
3914  // vectorcall adds the concept of a homogenous vector aggregate, similar to
3915  // other targets.
3916  if ((IsVectorCall || IsRegCall) &&
3917  isHomogeneousAggregate(Ty, Base, NumElts)) {
3918  if (IsRegCall) {
3919  if (FreeSSERegs >= NumElts) {
3920  FreeSSERegs -= NumElts;
3921  if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3922  return ABIArgInfo::getDirect();
3923  return ABIArgInfo::getExpand();
3924  }
3925  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3926  } else if (IsVectorCall) {
3927  if (FreeSSERegs >= NumElts &&
3928  (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3929  FreeSSERegs -= NumElts;
3930  return ABIArgInfo::getDirect();
3931  } else if (IsReturnType) {
3932  return ABIArgInfo::getExpand();
3933  } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3934  // HVAs are delayed and reclassified in the 2nd step.
3935  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3936  }
3937  }
3938  }
3939 
3940  if (Ty->isMemberPointerType()) {
3941  // If the member pointer is represented by an LLVM int or ptr, pass it
3942  // directly.
3943  llvm::Type *LLTy = CGT.ConvertType(Ty);
3944  if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3945  return ABIArgInfo::getDirect();
3946  }
3947 
3948  if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3949  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
3950  // not 1, 2, 4, or 8 bytes, must be passed by reference."
3951  if (Width > 64 || !llvm::isPowerOf2_64(Width))
3952  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
3953 
3954  // Otherwise, coerce it to a small integer.
3955  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Width));
3956  }
3957 
3958  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3959  switch (BT->getKind()) {
3960  case BuiltinType::Bool:
3961  // Bool type is always extended to the ABI, other builtin types are not
3962  // extended.
3963  return ABIArgInfo::getExtend(Ty);
3964 
3965  case BuiltinType::LongDouble:
3966  // Mingw64 GCC uses the old 80 bit extended precision floating point
3967  // unit. It passes them indirectly through memory.
3968  if (IsMingw64) {
3969  const llvm::fltSemantics *LDF = &getTarget().getLongDoubleFormat();
3970  if (LDF == &llvm::APFloat::x87DoubleExtended())
3971  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3972  }
3973  break;
3974 
3975  case BuiltinType::Int128:
3976  case BuiltinType::UInt128:
3977  // If it's a parameter type, the normal ABI rule is that arguments larger
3978  // than 8 bytes are passed indirectly. GCC follows it. We follow it too,
3979  // even though it isn't particularly efficient.
3980  if (!IsReturnType)
3981  return ABIArgInfo::getIndirect(Align, /*ByVal=*/false);
3982 
3983  // Mingw64 GCC returns i128 in XMM0. Coerce to v2i64 to handle that.
3984  // Clang matches them for compatibility.
3985  return ABIArgInfo::getDirect(
3986  llvm::VectorType::get(llvm::Type::getInt64Ty(getVMContext()), 2));
3987 
3988  default:
3989  break;
3990  }
3991  }
3992 
3993  return ABIArgInfo::getDirect();
3994 }
3995 
3996 void WinX86_64ABIInfo::computeVectorCallArgs(CGFunctionInfo &FI,
3997  unsigned FreeSSERegs,
3998  bool IsVectorCall,
3999  bool IsRegCall) const {
4000  unsigned Count = 0;
4001  for (auto &I : FI.arguments()) {
4002  // Vectorcall in x64 only permits the first 6 arguments to be passed
4003  // as XMM/YMM registers.
4004  if (Count < VectorcallMaxParamNumAsReg)
4005  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4006  else {
4007  // Since these cannot be passed in registers, pretend no registers
4008  // are left.
4009  unsigned ZeroSSERegsAvail = 0;
4010  I.info = classify(I.type, /*FreeSSERegs=*/ZeroSSERegsAvail, false,
4011  IsVectorCall, IsRegCall);
4012  }
4013  ++Count;
4014  }
4015 
4016  for (auto &I : FI.arguments()) {
4017  I.info = reclassifyHvaArgType(I.type, FreeSSERegs, I.info);
4018  }
4019 }
4020 
4021 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
4022  bool IsVectorCall =
4023  FI.getCallingConvention() == llvm::CallingConv::X86_VectorCall;
4024  bool IsRegCall = FI.getCallingConvention() == llvm::CallingConv::X86_RegCall;
4025 
4026  unsigned FreeSSERegs = 0;
4027  if (IsVectorCall) {
4028  // We can use up to 4 SSE return registers with vectorcall.
4029  FreeSSERegs = 4;
4030  } else if (IsRegCall) {
4031  // RegCall gives us 16 SSE registers.
4032  FreeSSERegs = 16;
4033  }
4034 
4035  if (!getCXXABI().classifyReturnType(FI))
4036  FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
4037  IsVectorCall, IsRegCall);
4038 
4039  if (IsVectorCall) {
4040  // We can use up to 6 SSE register parameters with vectorcall.
4041  FreeSSERegs = 6;
4042  } else if (IsRegCall) {
4043  // RegCall gives us 16 SSE registers, we can reuse the return registers.
4044  FreeSSERegs = 16;
4045  }
4046 
4047  if (IsVectorCall) {
4048  computeVectorCallArgs(FI, FreeSSERegs, IsVectorCall, IsRegCall);
4049  } else {
4050  for (auto &I : FI.arguments())
4051  I.info = classify(I.type, FreeSSERegs, false, IsVectorCall, IsRegCall);
4052  }
4053 
4054 }
4055 
4056 Address WinX86_64ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4057  QualType Ty) const {
4058 
4059  bool IsIndirect = false;
4060 
4061  // MS x64 ABI requirement: "Any argument that doesn't fit in 8 bytes, or is
4062  // not 1, 2, 4, or 8 bytes, must be passed by reference."
4063  if (isAggregateTypeForABI(Ty) || Ty->isMemberPointerType()) {
4064  uint64_t Width = getContext().getTypeSize(Ty);
4065  IsIndirect = Width > 64 || !llvm::isPowerOf2_64(Width);
4066  }
4067 
4068  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
4069  CGF.getContext().getTypeInfoInChars(Ty),
4071  /*allowHigherAlign*/ false);
4072 }
4073 
4074 // PowerPC-32
4075 namespace {
4076 /// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
4077 class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
4078  bool IsSoftFloatABI;
4079 
4080  CharUnits getParamTypeAlignment(QualType Ty) const;
4081 
4082 public:
4083  PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
4084  : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
4085 
4086  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4087  QualType Ty) const override;
4088 };
4089 
4090 class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
4091 public:
4092  PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
4093  : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
4094 
4095  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4096  // This is recovered from gcc output.
4097  return 1; // r1 is the dedicated stack pointer
4098  }
4099 
4100  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4101  llvm::Value *Address) const override;
4102 };
4103 }
4104 
4105 CharUnits PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4106  // Complex types are passed just like their elements
4107  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4108  Ty = CTy->getElementType();
4109 
4110  if (Ty->isVectorType())
4111  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16
4112  : 4);
4113 
4114  // For single-element float/vector structs, we consider the whole type
4115  // to have the same alignment requirements as its single element.
4116  const Type *AlignTy = nullptr;
4117  if (const Type *EltType = isSingleElementStruct(Ty, getContext())) {
4118  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4119  if ((EltType->isVectorType() && getContext().getTypeSize(EltType) == 128) ||
4120  (BT && BT->isFloatingPoint()))
4121  AlignTy = EltType;
4122  }
4123 
4124  if (AlignTy)
4125  return CharUnits::fromQuantity(AlignTy->isVectorType() ? 16 : 4);
4126  return CharUnits::fromQuantity(4);
4127 }
4128 
4129 // TODO: this implementation is now likely redundant with
4130 // DefaultABIInfo::EmitVAArg.
4131 Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
4132  QualType Ty) const {
4133  if (getTarget().getTriple().isOSDarwin()) {
4134  auto TI = getContext().getTypeInfoInChars(Ty);
4135  TI.second = getParamTypeAlignment(Ty);
4136 
4137  CharUnits SlotSize = CharUnits::fromQuantity(4);
4138  return emitVoidPtrVAArg(CGF, VAList, Ty,
4139  classifyArgumentType(Ty).isIndirect(), TI, SlotSize,
4140  /*AllowHigherAlign=*/true);
4141  }
4142 
4143  const unsigned OverflowLimit = 8;
4144  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4145  // TODO: Implement this. For now ignore.
4146  (void)CTy;
4147  return Address::invalid(); // FIXME?
4148  }
4149 
4150  // struct __va_list_tag {
4151  // unsigned char gpr;
4152  // unsigned char fpr;
4153  // unsigned short reserved;
4154  // void *overflow_arg_area;
4155  // void *reg_save_area;
4156  // };
4157 
4158  bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;
4159  bool isInt =
4160  Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();
4161  bool isF64 = Ty->isFloatingType() && getContext().getTypeSize(Ty) == 64;
4162 
4163  // All aggregates are passed indirectly? That doesn't seem consistent
4164  // with the argument-lowering code.
4165  bool isIndirect = Ty->isAggregateType();
4166 
4167  CGBuilderTy &Builder = CGF.Builder;
4168 
4169  // The calling convention either uses 1-2 GPRs or 1 FPR.
4170  Address NumRegsAddr = Address::invalid();
4171  if (isInt || IsSoftFloatABI) {
4172  NumRegsAddr = Builder.CreateStructGEP(VAList, 0, CharUnits::Zero(), "gpr");
4173  } else {
4174  NumRegsAddr = Builder.CreateStructGEP(VAList, 1, CharUnits::One(), "fpr");
4175  }
4176 
4177  llvm::Value *NumRegs = Builder.CreateLoad(NumRegsAddr, "numUsedRegs");
4178 
4179  // "Align" the register count when TY is i64.
4180  if (isI64 || (isF64 && IsSoftFloatABI)) {
4181  NumRegs = Builder.CreateAdd(NumRegs, Builder.getInt8(1));
4182  NumRegs = Builder.CreateAnd(NumRegs, Builder.getInt8((uint8_t) ~1U));
4183  }
4184 
4185  llvm::Value *CC =
4186  Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
4187 
4188  llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
4189  llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
4190  llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");
4191 
4192  Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);
4193 
4194  llvm::Type *DirectTy = CGF.ConvertType(Ty);
4195  if (isIndirect) DirectTy = DirectTy->getPointerTo(0);
4196 
4197  // Case 1: consume registers.
4198  Address RegAddr = Address::invalid();
4199  {
4200  CGF.EmitBlock(UsingRegs);
4201 
4202  Address RegSaveAreaPtr =
4203  Builder.CreateStructGEP(VAList, 4, CharUnits::fromQuantity(8));
4204  RegAddr = Address(Builder.CreateLoad(RegSaveAreaPtr),
4206  assert(RegAddr.getElementType() == CGF.Int8Ty);
4207 
4208  // Floating-point registers start after the general-purpose registers.
4209  if (!(isInt || IsSoftFloatABI)) {
4210  RegAddr = Builder.CreateConstInBoundsByteGEP(RegAddr,
4212  }
4213 
4214  // Get the address of the saved value by scaling the number of
4215  // registers we've used by the number of
4216  CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4217  llvm::Value *RegOffset =
4218  Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4219  RegAddr = Address(Builder.CreateInBoundsGEP(CGF.Int8Ty,
4220  RegAddr.getPointer(), RegOffset),
4221  RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
4222  RegAddr = Builder.CreateElementBitCast(RegAddr, DirectTy);
4223 
4224  // Increase the used-register count.
4225  NumRegs =
4226  Builder.CreateAdd(NumRegs,
4227  Builder.getInt8((isI64 || (isF64 && IsSoftFloatABI)) ? 2 : 1));
4228  Builder.CreateStore(NumRegs, NumRegsAddr);
4229 
4230  CGF.EmitBranch(Cont);
4231  }
4232 
4233  // Case 2: consume space in the overflow area.
4234  Address MemAddr = Address::invalid();
4235  {
4236  CGF.EmitBlock(UsingOverflow);
4237 
4238  Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
4239 
4240  // Everything in the overflow area is rounded up to a size of at least 4.
4241  CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
4242 
4243  CharUnits Size;
4244  if (!isIndirect) {
4245  auto TypeInfo = CGF.getContext().getTypeInfoInChars(Ty);
4246  Size = TypeInfo.first.alignTo(OverflowAreaAlign);
4247  } else {
4248  Size = CGF.getPointerSize();
4249  }
4250 
4251  Address OverflowAreaAddr =
4252  Builder.CreateStructGEP(VAList, 3, CharUnits::fromQuantity(4));
4253  Address OverflowArea(Builder.CreateLoad(OverflowAreaAddr, "argp.cur"),
4254  OverflowAreaAlign);
4255  // Round up address of argument to alignment
4256  CharUnits Align = CGF.getContext().getTypeAlignInChars(Ty);
4257  if (Align > OverflowAreaAlign) {
4258  llvm::Value *Ptr = OverflowArea.getPointer();
4259  OverflowArea = Address(emitRoundPointerUpToAlignment(CGF, Ptr, Align),
4260  Align);
4261  }
4262 
4263  MemAddr = Builder.CreateElementBitCast(OverflowArea, DirectTy);
4264 
4265  // Increase the overflow area.
4266  OverflowArea = Builder.CreateConstInBoundsByteGEP(OverflowArea, Size);
4267  Builder.CreateStore(OverflowArea.getPointer(), OverflowAreaAddr);
4268  CGF.EmitBranch(Cont);
4269  }
4270 
4271  CGF.EmitBlock(Cont);
4272 
4273  // Merge the cases with a phi.
4274  Address Result = emitMergePHI(CGF, RegAddr, UsingRegs, MemAddr, UsingOverflow,
4275  "vaarg.addr");
4276 
4277  // Load the pointer if the argument was passed indirectly.
4278  if (isIndirect) {
4279  Result = Address(Builder.CreateLoad(Result, "aggr"),
4281  }
4282 
4283  return Result;
4284 }
4285 
4286 bool
4287 PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4288  llvm::Value *Address) const {
4289  // This is calculated from the LLVM and GCC tables and verified
4290  // against gcc output. AFAIK all ABIs use the same encoding.
4291 
4292  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4293 
4294  llvm::IntegerType *i8 = CGF.Int8Ty;
4295  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4296  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4297  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4298 
4299  // 0-31: r0-31, the 4-byte general-purpose registers
4300  AssignToArrayRange(Builder, Address, Four8, 0, 31);
4301 
4302  // 32-63: fp0-31, the 8-byte floating-point registers
4303  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4304 
4305  // 64-76 are various 4-byte special-purpose registers:
4306  // 64: mq
4307  // 65: lr
4308  // 66: ctr
4309  // 67: ap
4310  // 68-75 cr0-7
4311  // 76: xer
4312  AssignToArrayRange(Builder, Address, Four8, 64, 76);
4313 
4314  // 77-108: v0-31, the 16-byte vector registers
4315  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4316 
4317  // 109: vrsave
4318  // 110: vscr
4319  // 111: spe_acc
4320  // 112: spefscr
4321  // 113: sfp
4322  AssignToArrayRange(Builder, Address, Four8, 109, 113);
4323 
4324  return false;
4325 }
4326 
4327 // PowerPC-64
4328 
4329 namespace {
4330 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
4331 class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
4332 public:
4333  enum ABIKind {
4334  ELFv1 = 0,
4335  ELFv2
4336  };
4337 
4338 private:
4339  static const unsigned GPRBits = 64;
4340  ABIKind Kind;
4341  bool HasQPX;
4342  bool IsSoftFloatABI;
4343 
4344  // A vector of float or double will be promoted to <4 x f32> or <4 x f64> and
4345  // will be passed in a QPX register.
4346  bool IsQPXVectorTy(const Type *Ty) const {
4347  if (!HasQPX)
4348  return false;
4349 
4350  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4351  unsigned NumElements = VT->getNumElements();
4352  if (NumElements == 1)
4353  return false;
4354 
4355  if (VT->getElementType()->isSpecificBuiltinType(BuiltinType::Double)) {
4356  if (getContext().getTypeSize(Ty) <= 256)
4357  return true;
4358  } else if (VT->getElementType()->
4359  isSpecificBuiltinType(BuiltinType::Float)) {
4360  if (getContext().getTypeSize(Ty) <= 128)
4361  return true;
4362  }
4363  }
4364 
4365  return false;
4366  }
4367 
4368  bool IsQPXVectorTy(QualType Ty) const {
4369  return IsQPXVectorTy(Ty.getTypePtr());
4370  }
4371 
4372 public:
4373  PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
4374  bool SoftFloatABI)
4375  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
4376  IsSoftFloatABI(SoftFloatABI) {}
4377 
4378  bool isPromotableTypeForABI(QualType Ty) const;
4379  CharUnits getParamTypeAlignment(QualType Ty) const;
4380 
4381  ABIArgInfo classifyReturnType(QualType RetTy) const;
4383 
4384  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4385  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4386  uint64_t Members) const override;
4387 
4388  // TODO: We can add more logic to computeInfo to improve performance.
4389  // Example: For aggregate arguments that fit in a register, we could
4390  // use getDirectInReg (as is done below for structs containing a single
4391  // floating-point value) to avoid pushing them to memory on function
4392  // entry. This would require changing the logic in PPCISelLowering
4393  // when lowering the parameters in the caller and args in the callee.
4394  void computeInfo(CGFunctionInfo &FI) const override {
4395  if (!getCXXABI().classifyReturnType(FI))
4397  for (auto &I : FI.arguments()) {
4398  // We rely on the default argument classification for the most part.
4399  // One exception: An aggregate containing a single floating-point
4400  // or vector item must be passed in a register if one is available.
4401  const Type *T = isSingleElementStruct(I.type, getContext());
4402  if (T) {
4403  const BuiltinType *BT = T->getAs<BuiltinType>();
4404  if (IsQPXVectorTy(T) ||
4405  (T->isVectorType() && getContext().getTypeSize(T) == 128) ||
4406  (BT && BT->isFloatingPoint())) {
4407  QualType QT(T, 0);
4408  I.info = ABIArgInfo::getDirectInReg(CGT.ConvertType(QT));
4409  continue;
4410  }
4411  }
4412  I.info = classifyArgumentType(I.type);
4413  }
4414  }
4415 
4416  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4417  QualType Ty) const override;
4418 
4419  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4420  bool asReturnValue) const override {
4421  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4422  }
4423 
4424  bool isSwiftErrorInRegister() const override {
4425  return false;
4426  }
4427 };
4428 
4429 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
4430 
4431 public:
4432  PPC64_SVR4_TargetCodeGenInfo(CodeGenTypes &CGT,
4433  PPC64_SVR4_ABIInfo::ABIKind Kind, bool HasQPX,
4434  bool SoftFloatABI)
4435  : TargetCodeGenInfo(new PPC64_SVR4_ABIInfo(CGT, Kind, HasQPX,
4436  SoftFloatABI)) {}
4437 
4438  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4439  // This is recovered from gcc output.
4440  return 1; // r1 is the dedicated stack pointer
4441  }
4442 
4443  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4444  llvm::Value *Address) const override;
4445 };
4446 
4447 class PPC64TargetCodeGenInfo : public DefaultTargetCodeGenInfo {
4448 public:
4449  PPC64TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}
4450 
4451  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
4452  // This is recovered from gcc output.
4453  return 1; // r1 is the dedicated stack pointer
4454  }
4455 
4456  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4457  llvm::Value *Address) const override;
4458 };
4459 
4460 }
4461 
4462 // Return true if the ABI requires Ty to be passed sign- or zero-
4463 // extended to 64 bits.
4464 bool
4465 PPC64_SVR4_ABIInfo::isPromotableTypeForABI(QualType Ty) const {
4466  // Treat an enum type as its underlying type.
4467  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
4468  Ty = EnumTy->getDecl()->getIntegerType();
4469 
4470  // Promotable integer types are required to be promoted by the ABI.
4471  if (Ty->isPromotableIntegerType())
4472  return true;
4473 
4474  // In addition to the usual promotable integer types, we also need to
4475  // extend all 32-bit types, since the ABI requires promotion to 64 bits.
4476  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
4477  switch (BT->getKind()) {
4478  case BuiltinType::Int:
4479  case BuiltinType::UInt:
4480  return true;
4481  default:
4482  break;
4483  }
4484 
4485  return false;
4486 }
4487 
4488 /// isAlignedParamType - Determine whether a type requires 16-byte or
4489 /// higher alignment in the parameter area. Always returns at least 8.
4490 CharUnits PPC64_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
4491  // Complex types are passed just like their elements.
4492  if (const ComplexType *CTy = Ty->getAs<ComplexType>())
4493  Ty = CTy->getElementType();
4494 
4495  // Only vector types of size 16 bytes need alignment (larger types are
4496  // passed via reference, smaller types are not aligned).
4497  if (IsQPXVectorTy(Ty)) {
4498  if (getContext().getTypeSize(Ty) > 128)
4499  return CharUnits::fromQuantity(32);
4500 
4501  return CharUnits::fromQuantity(16);
4502  } else if (Ty->isVectorType()) {
4503  return CharUnits::fromQuantity(getContext().getTypeSize(Ty) == 128 ? 16 : 8);
4504  }
4505 
4506  // For single-element float/vector structs, we consider the whole type
4507  // to have the same alignment requirements as its single element.
4508  const Type *AlignAsType = nullptr;
4509  const Type *EltType = isSingleElementStruct(Ty, getContext());
4510  if (EltType) {
4511  const BuiltinType *BT = EltType->getAs<BuiltinType>();
4512  if (IsQPXVectorTy(EltType) || (EltType->isVectorType() &&
4513  getContext().getTypeSize(EltType) == 128) ||
4514  (BT && BT->isFloatingPoint()))
4515  AlignAsType = EltType;
4516  }
4517 
4518  // Likewise for ELFv2 homogeneous aggregates.
4519  const Type *Base = nullptr;
4520  uint64_t Members = 0;
4521  if (!AlignAsType && Kind == ELFv2 &&
4522  isAggregateTypeForABI(Ty) && isHomogeneousAggregate(Ty, Base, Members))
4523  AlignAsType = Base;
4524 
4525  // With special case aggregates, only vector base types need alignment.
4526  if (AlignAsType && IsQPXVectorTy(AlignAsType)) {
4527  if (getContext().getTypeSize(AlignAsType) > 128)
4528  return CharUnits::fromQuantity(32);
4529 
4530  return CharUnits::fromQuantity(16);
4531  } else if (AlignAsType) {
4532  return CharUnits::fromQuantity(AlignAsType->isVectorType() ? 16 : 8);
4533  }
4534 
4535  // Otherwise, we only need alignment for any aggregate type that
4536  // has an alignment requirement of >= 16 bytes.
4537  if (isAggregateTypeForABI(Ty) && getContext().getTypeAlign(Ty) >= 128) {
4538  if (HasQPX && getContext().getTypeAlign(Ty) >= 256)
4539  return CharUnits::fromQuantity(32);
4540  return CharUnits::fromQuantity(16);
4541  }
4542 
4543  return CharUnits::fromQuantity(8);
4544 }
4545 
4546 /// isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous
4547 /// aggregate. Base is set to the base element type, and Members is set
4548 /// to the number of base elements.
4550  uint64_t &Members) const {
4551  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
4552  uint64_t NElements = AT->getSize().getZExtValue();
4553  if (NElements == 0)
4554  return false;
4555  if (!isHomogeneousAggregate(AT->getElementType(), Base, Members))
4556  return false;
4557  Members *= NElements;
4558  } else if (const RecordType *RT = Ty->getAs<RecordType>()) {
4559  const RecordDecl *RD = RT->getDecl();
4560  if (RD->hasFlexibleArrayMember())
4561  return false;
4562 
4563  Members = 0;
4564 
4565  // If this is a C++ record, check the bases first.
4566  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
4567  for (const auto &I : CXXRD->bases()) {
4568  // Ignore empty records.
4569  if (isEmptyRecord(getContext(), I.getType(), true))
4570  continue;
4571 
4572  uint64_t FldMembers;
4573  if (!isHomogeneousAggregate(I.getType(), Base, FldMembers))
4574  return false;
4575 
4576  Members += FldMembers;
4577  }
4578  }
4579 
4580  for (const auto *FD : RD->fields()) {
4581  // Ignore (non-zero arrays of) empty records.
4582  QualType FT = FD->getType();
4583  while (const ConstantArrayType *AT =
4584  getContext().getAsConstantArrayType(FT)) {
4585  if (AT->getSize().getZExtValue() == 0)
4586  return false;
4587  FT = AT->getElementType();
4588  }
4589  if (isEmptyRecord(getContext(), FT, true))
4590  continue;
4591 
4592  // For compatibility with GCC, ignore empty bitfields in C++ mode.
4593  if (getContext().getLangOpts().CPlusPlus &&
4594  FD->isZeroLengthBitField(getContext()))
4595  continue;
4596 
4597  uint64_t FldMembers;
4598  if (!isHomogeneousAggregate(FD->getType(), Base, FldMembers))
4599  return false;
4600 
4601  Members = (RD->isUnion() ?
4602  std::max(Members, FldMembers) : Members + FldMembers);
4603  }
4604 
4605  if (!Base)
4606  return false;
4607 
4608  // Ensure there is no padding.
4609  if (getContext().getTypeSize(Base) * Members !=
4610  getContext().getTypeSize(Ty))
4611  return false;
4612  } else {
4613  Members = 1;
4614  if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
4615  Members = 2;
4616  Ty = CT->getElementType();
4617  }
4618 
4619  // Most ABIs only support float, double, and some vector type widths.
4621  return false;
4622 
4623  // The base type must be the same for all members. Types that
4624  // agree in both total size and mode (float vs. vector) are
4625  // treated as being equivalent here.
4626  const Type *TyPtr = Ty.getTypePtr();
4627  if (!Base) {
4628  Base = TyPtr;
4629  // If it's a non-power-of-2 vector, its size is already a power-of-2,
4630  // so make sure to widen it explicitly.
4631  if (const VectorType *VT = Base->getAs<VectorType>()) {
4632  QualType EltTy = VT->getElementType();
4633  unsigned NumElements =
4634  getContext().getTypeSize(VT) / getContext().getTypeSize(EltTy);
4635  Base = getContext()
4636  .getVectorType(EltTy, NumElements, VT->getVectorKind())
4637  .getTypePtr();
4638  }
4639  }
4640 
4641  if (Base->isVectorType() != TyPtr->isVectorType() ||
4642  getContext().getTypeSize(Base) != getContext().getTypeSize(TyPtr))
4643  return false;
4644  }
4645  return Members > 0 && isHomogeneousAggregateSmallEnough(Base, Members);
4646 }
4647 
4648 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
4649  // Homogeneous aggregates for ELFv2 must have base types of float,
4650  // double, long double, or 128-bit vectors.
4651  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
4652  if (BT->getKind() == BuiltinType::Float ||
4653  BT->getKind() == BuiltinType::Double ||
4654  BT->getKind() == BuiltinType::LongDouble ||
4656  (BT->getKind() == BuiltinType::Float128))) {
4657  if (IsSoftFloatABI)
4658  return false;
4659  return true;
4660  }
4661  }
4662  if (const VectorType *VT = Ty->getAs<VectorType>()) {
4663  if (getContext().getTypeSize(VT) == 128 || IsQPXVectorTy(Ty))
4664  return true;
4665  }
4666  return false;
4667 }
4668 
4669 bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
4670  const Type *Base, uint64_t Members) const {
4671  // Vector and fp128 types require one register, other floating point types
4672  // require one or two registers depending on their size.
4673  uint32_t NumRegs =
4675  Base->isFloat128Type()) ||
4676  Base->isVectorType()) ? 1
4677  : (getContext().getTypeSize(Base) + 63) / 64;
4678 
4679  // Homogeneous Aggregates may occupy at most 8 registers.
4680  return Members * NumRegs <= 8;
4681 }
4682 
4683 ABIArgInfo
4686 
4687  if (Ty->isAnyComplexType())
4688  return ABIArgInfo::getDirect();
4689 
4690  // Non-Altivec vector types are passed in GPRs (smaller than 16 bytes)
4691  // or via reference (larger than 16 bytes).
4692  if (Ty->isVectorType() && !IsQPXVectorTy(Ty)) {
4693  uint64_t Size = getContext().getTypeSize(Ty);
4694  if (Size > 128)
4695  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
4696  else if (Size < 128) {
4697  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4698  return ABIArgInfo::getDirect(CoerceTy);
4699  }
4700  }
4701 
4702  if (isAggregateTypeForABI(Ty)) {
4705 
4706  uint64_t ABIAlign = getParamTypeAlignment(Ty).getQuantity();
4707  uint64_t TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
4708 
4709  // ELFv2 homogeneous aggregates are passed as array types.
4710  const Type *Base = nullptr;
4711  uint64_t Members = 0;
4712  if (Kind == ELFv2 &&
4713  isHomogeneousAggregate(Ty, Base, Members)) {
4714  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4715  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4716  return ABIArgInfo::getDirect(CoerceTy);
4717  }
4718 
4719  // If an aggregate may end up fully in registers, we do not
4720  // use the ByVal method, but pass the aggregate as array.
4721  // This is usually beneficial since we avoid forcing the
4722  // back-end to store the argument to memory.
4723  uint64_t Bits = getContext().getTypeSize(Ty);
4724  if (Bits > 0 && Bits <= 8 * GPRBits) {
4725  llvm::Type *CoerceTy;
4726 
4727  // Types up to 8 bytes are passed as integer type (which will be
4728  // properly aligned in the argument save area doubleword).
4729  if (Bits <= GPRBits)
4730  CoerceTy =
4731  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4732  // Larger types are passed as arrays, with the base type selected
4733  // according to the required alignment in the save area.
4734  else {
4735  uint64_t RegBits = ABIAlign * 8;
4736  uint64_t NumRegs = llvm::alignTo(Bits, RegBits) / RegBits;
4737  llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits);
4738  CoerceTy = llvm::ArrayType::get(RegTy, NumRegs);
4739  }
4740 
4741  return ABIArgInfo::getDirect(CoerceTy);
4742  }
4743 
4744  // All other aggregates are passed ByVal.
4746  /*ByVal=*/true,
4747  /*Realign=*/TyAlign > ABIAlign);
4748  }
4749 
4750  return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
4751  : ABIArgInfo::getDirect());
4752 }
4753 
4754 ABIArgInfo
4756  if (RetTy->isVoidType())
4757  return ABIArgInfo::getIgnore();
4758 
4759  if (RetTy->isAnyComplexType())
4760  return ABIArgInfo::getDirect();
4761 
4762  // Non-Altivec vector types are returned in GPRs (smaller than 16 bytes)
4763  // or via reference (larger than 16 bytes).
4764  if (RetTy->isVectorType() && !IsQPXVectorTy(RetTy)) {
4765  uint64_t Size = getContext().getTypeSize(RetTy);
4766  if (Size > 128)
4767  return getNaturalAlignIndirect(RetTy);
4768  else if (Size < 128) {
4769  llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(), Size);
4770  return ABIArgInfo::getDirect(CoerceTy);
4771  }
4772  }
4773 
4774  if (isAggregateTypeForABI(RetTy)) {
4775  // ELFv2 homogeneous aggregates are returned as array types.
4776  const Type *Base = nullptr;
4777  uint64_t Members = 0;
4778  if (Kind == ELFv2 &&
4779  isHomogeneousAggregate(RetTy, Base, Members)) {
4780  llvm::Type *BaseTy = CGT.ConvertType(QualType(Base, 0));
4781  llvm::Type *CoerceTy = llvm::ArrayType::get(BaseTy, Members);
4782  return ABIArgInfo::getDirect(CoerceTy);
4783  }
4784 
4785  // ELFv2 small aggregates are returned in up to two registers.
4786  uint64_t Bits = getContext().getTypeSize(RetTy);
4787  if (Kind == ELFv2 && Bits <= 2 * GPRBits) {
4788  if (Bits == 0)
4789  return ABIArgInfo::getIgnore();
4790 
4791  llvm::Type *CoerceTy;
4792  if (Bits > GPRBits) {
4793  CoerceTy = llvm::IntegerType::get(getVMContext(), GPRBits);
4794  CoerceTy = llvm::StructType::get(CoerceTy, CoerceTy);
4795  } else
4796  CoerceTy =
4797  llvm::IntegerType::get(getVMContext(), llvm::alignTo(Bits, 8));
4798  return ABIArgInfo::getDirect(CoerceTy);
4799  }
4800 
4801  // All other aggregates are returned indirectly.
4802  return getNaturalAlignIndirect(RetTy);
4803  }
4804 
4805  return (isPromotableTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
4806  : ABIArgInfo::getDirect());
4807 }
4808 
4809 // Based on ARMABIInfo::EmitVAArg, adjusted for 64-bit machine.
4810 Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4811  QualType Ty) const {
4812  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
4813  TypeInfo.second = getParamTypeAlignment(Ty);
4814 
4815  CharUnits SlotSize = CharUnits::fromQuantity(8);
4816 
4817  // If we have a complex type and the base type is smaller than 8 bytes,
4818  // the ABI calls for the real and imaginary parts to be right-adjusted
4819  // in separate doublewords. However, Clang expects us to produce a
4820  // pointer to a structure with the two parts packed tightly. So generate
4821  // loads of the real and imaginary parts relative to the va_list pointer,
4822  // and store them to a temporary structure.
4823  if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
4824  CharUnits EltSize = TypeInfo.first / 2;
4825  if (EltSize < SlotSize) {
4826  Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty,
4827  SlotSize * 2, SlotSize,
4828  SlotSize, /*AllowHigher*/ true);
4829 
4830  Address RealAddr = Addr;
4831  Address ImagAddr = RealAddr;
4832  if (CGF.CGM.getDataLayout().isBigEndian()) {
4833  RealAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr,
4834  SlotSize - EltSize);
4835  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr,
4836  2 * SlotSize - EltSize);
4837  } else {
4838  ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize);
4839  }
4840 
4841  llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType());
4842  RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy);
4843  ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy);
4844  llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal");
4845  llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag");
4846 
4847  Address Temp = CGF.CreateMemTemp(Ty, "vacplx");
4848  CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty),
4849  /*init*/ true);
4850  return Temp;
4851  }
4852  }
4853 
4854  // Otherwise, just use the general rule.
4855  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
4856  TypeInfo, SlotSize, /*AllowHigher*/ true);
4857 }
4858 
4859 static bool
4861  llvm::Value *Address) {
4862  // This is calculated from the LLVM and GCC tables and verified
4863  // against gcc output. AFAIK all ABIs use the same encoding.
4864 
4865  CodeGen::CGBuilderTy &Builder = CGF.Builder;
4866 
4867  llvm::IntegerType *i8 = CGF.Int8Ty;
4868  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
4869  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
4870  llvm::Value *Sixteen8 = llvm::ConstantInt::get(i8, 16);
4871 
4872  // 0-31: r0-31, the 8-byte general-purpose registers
4873  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
4874 
4875  // 32-63: fp0-31, the 8-byte floating-point registers
4876  AssignToArrayRange(Builder, Address, Eight8, 32, 63);
4877 
4878  // 64-67 are various 8-byte special-purpose registers:
4879  // 64: mq
4880  // 65: lr
4881  // 66: ctr
4882  // 67: ap
4883  AssignToArrayRange(Builder, Address, Eight8, 64, 67);
4884 
4885  // 68-76 are various 4-byte special-purpose registers:
4886  // 68-75 cr0-7
4887  // 76: xer
4888  AssignToArrayRange(Builder, Address, Four8, 68, 76);
4889 
4890  // 77-108: v0-31, the 16-byte vector registers
4891  AssignToArrayRange(Builder, Address, Sixteen8, 77, 108);
4892 
4893  // 109: vrsave
4894  // 110: vscr
4895  // 111: spe_acc
4896  // 112: spefscr
4897  // 113: sfp
4898  // 114: tfhar
4899  // 115: tfiar
4900  // 116: texasr
4901  AssignToArrayRange(Builder, Address, Eight8, 109, 116);
4902 
4903  return false;
4904 }
4905 
4906 bool
4907 PPC64_SVR4_TargetCodeGenInfo::initDwarfEHRegSizeTable(
4909  llvm::Value *Address) const {
4910 
4911  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4912 }
4913 
4914 bool
4915 PPC64TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
4916  llvm::Value *Address) const {
4917 
4918  return PPC64_initDwarfEHRegSizeTable(CGF, Address);
4919 }
4920 
4921 //===----------------------------------------------------------------------===//
4922 // AArch64 ABI Implementation
4923 //===----------------------------------------------------------------------===//
4924 
4925 namespace {
4926 
4927 class AArch64ABIInfo : public SwiftABIInfo {
4928 public:
4929  enum ABIKind {
4930  AAPCS = 0,
4931  DarwinPCS,
4932  Win64
4933  };
4934 
4935 private:
4936  ABIKind Kind;
4937 
4938 public:
4939  AArch64ABIInfo(CodeGenTypes &CGT, ABIKind Kind)
4940  : SwiftABIInfo(CGT), Kind(Kind) {}
4941 
4942 private:
4943  ABIKind getABIKind() const { return Kind; }
4944  bool isDarwinPCS() const { return Kind == DarwinPCS; }
4945 
4946  ABIArgInfo classifyReturnType(QualType RetTy) const;
4948  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
4949  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
4950  uint64_t Members) const override;
4951 
4952  bool isIllegalVectorType(QualType Ty) const;
4953 
4954  void computeInfo(CGFunctionInfo &FI) const override {
4955  if (!::classifyReturnType(getCXXABI(), FI, *this))
4957 
4958  for (auto &it : FI.arguments())
4959  it.info = classifyArgumentType(it.type);
4960  }
4961 
4962  Address EmitDarwinVAArg(Address VAListAddr, QualType Ty,
4963  CodeGenFunction &CGF) const;
4964 
4965  Address EmitAAPCSVAArg(Address VAListAddr, QualType Ty,
4966  CodeGenFunction &CGF) const;
4967 
4968  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
4969  QualType Ty) const override {
4970  return Kind == Win64 ? EmitMSVAArg(CGF, VAListAddr, Ty)
4971  : isDarwinPCS() ? EmitDarwinVAArg(VAListAddr, Ty, CGF)
4972  : EmitAAPCSVAArg(VAListAddr, Ty, CGF);
4973  }
4974 
4975  Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
4976  QualType Ty) const override;
4977 
4978  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
4979  bool asReturnValue) const override {
4980  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
4981  }
4982  bool isSwiftErrorInRegister() const override {
4983  return true;
4984  }
4985 
4986  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
4987  unsigned elts) const override;
4988 };
4989 
4990 class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
4991 public:
4992  AArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind Kind)
4993  : TargetCodeGenInfo(new AArch64ABIInfo(CGT, Kind)) {}
4994 
4995  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
4996  return "mov\tfp, fp\t\t// marker for objc_retainAutoreleaseReturnValue";
4997  }
4998 
4999  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5000  return 31;
5001  }
5002 
5003  bool doesReturnSlotInterfereWithArgs() const override { return false; }
5004 
5005  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5006  CodeGen::CodeGenModule &CGM) const override {
5007  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5008  if (!FD)
5009  return;
5010  llvm::Function *Fn = cast<llvm::Function>(GV);
5011 
5012  auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
5014  Fn->addFnAttr("sign-return-address",
5016  ? "all"
5017  : "non-leaf");
5018 
5019  auto Key = CGM.getCodeGenOpts().getSignReturnAddressKey();
5020  Fn->addFnAttr("sign-return-address-key",
5021  Key == CodeGenOptions::SignReturnAddressKeyValue::AKey
5022  ? "a_key"
5023  : "b_key");
5024  }
5025 
5026  if (CGM.getCodeGenOpts().BranchTargetEnforcement)
5027  Fn->addFnAttr("branch-target-enforcement");
5028  }
5029 };
5030 
5031 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
5032 public:
5033  WindowsAArch64TargetCodeGenInfo(CodeGenTypes &CGT, AArch64ABIInfo::ABIKind K)
5034  : AArch64TargetCodeGenInfo(CGT, K) {}
5035 
5036  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5037  CodeGen::CodeGenModule &CGM) const override;
5038 
5039  void getDependentLibraryOption(llvm::StringRef Lib,
5040  llvm::SmallString<24> &Opt) const override {
5041  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5042  }
5043 
5044  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5045  llvm::SmallString<32> &Opt) const override {
5046  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5047  }
5048 };
5049 
5050 void WindowsAArch64TargetCodeGenInfo::setTargetAttributes(
5051  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5052  AArch64TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5053  if (GV->isDeclaration())
5054  return;
5055  addStackProbeTargetAttributes(D, GV, CGM);
5056 }
5057 }
5058 
5061 
5062  // Handle illegal vector types here.
5063  if (isIllegalVectorType(Ty)) {
5064  uint64_t Size = getContext().getTypeSize(Ty);
5065  // Android promotes <2 x i8> to i16, not i32
5066  if (isAndroid() && (Size <= 16)) {
5067  llvm::Type *ResType = llvm::Type::getInt16Ty(getVMContext());
5068  return ABIArgInfo::getDirect(ResType);
5069  }
5070  if (Size <= 32) {
5071  llvm::Type *ResType = llvm::Type::getInt32Ty(getVMContext());
5072  return ABIArgInfo::getDirect(ResType);
5073  }
5074  if (Size == 64) {
5075  llvm::Type *ResType =
5076  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 2);
5077  return ABIArgInfo::getDirect(ResType);
5078  }
5079  if (Size == 128) {
5080  llvm::Type *ResType =
5081  llvm::VectorType::get(llvm::Type::getInt32Ty(getVMContext()), 4);
5082  return ABIArgInfo::getDirect(ResType);
5083  }
5084  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5085  }
5086 
5087  if (!isAggregateTypeForABI(Ty)) {
5088  // Treat an enum type as its underlying type.
5089  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
5090  Ty = EnumTy->getDecl()->getIntegerType();
5091 
5092  return (Ty->isPromotableIntegerType() && isDarwinPCS()
5093  ? ABIArgInfo::getExtend(Ty)
5094  : ABIArgInfo::getDirect());
5095  }
5096 
5097  // Structures with either a non-trivial destructor or a non-trivial
5098  // copy constructor are always indirect.
5100  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
5102  }
5103 
5104  // Empty records are always ignored on Darwin, but actually passed in C++ mode
5105  // elsewhere for GNU compatibility.
5106  uint64_t Size = getContext().getTypeSize(Ty);
5107  bool IsEmpty = isEmptyRecord(getContext(), Ty, true);
5108  if (IsEmpty || Size == 0) {
5109  if (!getContext().getLangOpts().CPlusPlus || isDarwinPCS())
5110  return ABIArgInfo::getIgnore();
5111 
5112  // GNU C mode. The only argument that gets ignored is an empty one with size
5113  // 0.
5114  if (IsEmpty && Size == 0)
5115  return ABIArgInfo::getIgnore();
5116  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
5117  }
5118 
5119  // Homogeneous Floating-point Aggregates (HFAs) need to be expanded.
5120  const Type *Base = nullptr;
5121  uint64_t Members = 0;
5122  if (isHomogeneousAggregate(Ty, Base, Members)) {
5123  return ABIArgInfo::getDirect(
5124  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members));
5125  }
5126 
5127  // Aggregates <= 16 bytes are passed directly in registers or on the stack.
5128  if (Size <= 128) {
5129  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5130  // same size and alignment.
5131  if (getTarget().isRenderScriptTarget()) {
5132  return coerceToIntArray(Ty, getContext(), getVMContext());
5133  }
5134  unsigned Alignment;
5135  if (Kind == AArch64ABIInfo::AAPCS) {
5136  Alignment = getContext().getTypeUnadjustedAlign(Ty);
5137  Alignment = Alignment < 128 ? 64 : 128;
5138  } else {
5139  Alignment = getContext().getTypeAlign(Ty);
5140  }
5141  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5142 
5143  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5144  // For aggregates with 16-byte alignment, we use i128.
5145  if (Alignment < 128 && Size == 128) {
5146  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5147  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5148  }
5149  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5150  }
5151 
5152  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5153 }
5154 
5156  if (RetTy->isVoidType())
5157  return ABIArgInfo::getIgnore();
5158 
5159  // Large vector types should be returned via memory.
5160  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 128)
5161  return getNaturalAlignIndirect(RetTy);
5162 
5163  if (!isAggregateTypeForABI(RetTy)) {
5164  // Treat an enum type as its underlying type.
5165  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
5166  RetTy = EnumTy->getDecl()->getIntegerType();
5167 
5168  return (RetTy->isPromotableIntegerType() && isDarwinPCS()
5169  ? ABIArgInfo::getExtend(RetTy)
5170  : ABIArgInfo::getDirect());
5171  }
5172 
5173  uint64_t Size = getContext().getTypeSize(RetTy);
5174  if (isEmptyRecord(getContext(), RetTy, true) || Size == 0)
5175  return ABIArgInfo::getIgnore();
5176 
5177  const Type *Base = nullptr;
5178  uint64_t Members = 0;
5179  if (isHomogeneousAggregate(RetTy, Base, Members))
5180  // Homogeneous Floating-point Aggregates (HFAs) are returned directly.
5181  return ABIArgInfo::getDirect();
5182 
5183  // Aggregates <= 16 bytes are returned directly in registers or on the stack.
5184  if (Size <= 128) {
5185  // On RenderScript, coerce Aggregates <= 16 bytes to an integer array of
5186  // same size and alignment.
5187  if (getTarget().isRenderScriptTarget()) {
5188  return coerceToIntArray(RetTy, getContext(), getVMContext());
5189  }
5190  unsigned Alignment = getContext().getTypeAlign(RetTy);
5191  Size = llvm::alignTo(Size, 64); // round up to multiple of 8 bytes
5192 
5193  // We use a pair of i64 for 16-byte aggregate with 8-byte alignment.
5194  // For aggregates with 16-byte alignment, we use i128.
5195  if (Alignment < 128 && Size == 128) {
5196  llvm::Type *BaseTy = llvm::Type::getInt64Ty(getVMContext());
5197  return ABIArgInfo::getDirect(llvm::ArrayType::get(BaseTy, Size / 64));
5198  }
5199  return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), Size));
5200  }
5201 
5202  return getNaturalAlignIndirect(RetTy);
5203 }
5204 
5205 /// isIllegalVectorType - check whether the vector type is legal for AArch64.
5206 bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
5207  if (const VectorType *VT = Ty->getAs<VectorType>()) {
5208  // Check whether VT is legal.
5209  unsigned NumElements = VT->getNumElements();
5210  uint64_t Size = getContext().getTypeSize(VT);
5211  // NumElements should be power of 2.
5212  if (!llvm::isPowerOf2_32(NumElements))
5213  return true;
5214  return Size != 64 && (Size != 128 || NumElements == 1);
5215  }
5216  return false;
5217 }
5218 
5219 bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
5220  llvm::Type *eltTy,
5221  unsigned elts) const {
5222  if (!llvm::isPowerOf2_32(elts))
5223  return false;
5224  if (totalSize.getQuantity() != 8 &&
5225  (totalSize.getQuantity() != 16 || elts == 1))
5226  return false;
5227  return true;
5228 }
5229 
5230 bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
5231  // Homogeneous aggregates for AAPCS64 must have base types of a floating
5232  // point type or a short-vector type. This is the same as the 32-bit ABI,
5233  // but with the difference that any floating-point type is allowed,
5234  // including __fp16.
5235  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
5236  if (BT->isFloatingPoint())
5237  return true;
5238  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
5239  unsigned VecSize = getContext().getTypeSize(VT);
5240  if (VecSize == 64 || VecSize == 128)
5241  return true;
5242  }
5243  return false;
5244 }
5245 
5246 bool AArch64ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
5247  uint64_t Members) const {
5248  return Members <= 4;
5249 }
5250 
5251 Address AArch64ABIInfo::EmitAAPCSVAArg(Address VAListAddr,
5252  QualType Ty,
5253  CodeGenFunction &CGF) const {
5255  bool IsIndirect = AI.isIndirect();
5256 
5257  llvm::Type *BaseTy = CGF.ConvertType(Ty);
5258  if (IsIndirect)
5259  BaseTy = llvm::PointerType::getUnqual(BaseTy);
5260  else if (AI.getCoerceToType())
5261  BaseTy = AI.getCoerceToType();
5262 
5263  unsigned NumRegs = 1;
5264  if (llvm::ArrayType *ArrTy = dyn_cast<llvm::ArrayType>(BaseTy)) {
5265  BaseTy = ArrTy->getElementType();
5266  NumRegs = ArrTy->getNumElements();
5267  }
5268  bool IsFPR = BaseTy->isFloatingPointTy() || BaseTy->isVectorTy();
5269 
5270  // The AArch64 va_list type and handling is specified in the Procedure Call
5271  // Standard, section B.4:
5272  //
5273  // struct {
5274  // void *__stack;
5275  // void *__gr_top;
5276  // void *__vr_top;
5277  // int __gr_offs;
5278  // int __vr_offs;
5279  // };
5280 
5281  llvm::BasicBlock *MaybeRegBlock = CGF.createBasicBlock("vaarg.maybe_reg");
5282  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
5283  llvm::BasicBlock *OnStackBlock = CGF.createBasicBlock("vaarg.on_stack");
5284  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
5285 
5286  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5287  CharUnits TyAlign = TyInfo.second;
5288 
5289  Address reg_offs_p = Address::invalid();
5290  llvm::Value *reg_offs = nullptr;
5291  int reg_top_index;
5292  CharUnits reg_top_offset;
5293  int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity();
5294  if (!IsFPR) {
5295  // 3 is the field number of __gr_offs
5296  reg_offs_p =
5297  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
5298  "gr_offs_p");
5299  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "gr_offs");
5300  reg_top_index = 1; // field number for __gr_top
5301  reg_top_offset = CharUnits::fromQuantity(8);
5302  RegSize = llvm::alignTo(RegSize, 8);
5303  } else {
5304  // 4 is the field number of __vr_offs.
5305  reg_offs_p =
5306  CGF.Builder.CreateStructGEP(VAListAddr, 4, CharUnits::fromQuantity(28),
5307  "vr_offs_p");
5308  reg_offs = CGF.Builder.CreateLoad(reg_offs_p, "vr_offs");
5309  reg_top_index = 2; // field number for __vr_top
5310  reg_top_offset = CharUnits::fromQuantity(16);
5311  RegSize = 16 * NumRegs;
5312  }
5313 
5314  //=======================================
5315  // Find out where argument was passed
5316  //=======================================
5317 
5318  // If reg_offs >= 0 we're already using the stack for this type of
5319  // argument. We don't want to keep updating reg_offs (in case it overflows,
5320  // though anyone passing 2GB of arguments, each at most 16 bytes, deserves
5321  // whatever they get).
5322  llvm::Value *UsingStack = nullptr;
5323  UsingStack = CGF.Builder.CreateICmpSGE(
5324  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, 0));
5325 
5326  CGF.Builder.CreateCondBr(UsingStack, OnStackBlock, MaybeRegBlock);
5327 
5328  // Otherwise, at least some kind of argument could go in these registers, the
5329  // question is whether this particular type is too big.
5330  CGF.EmitBlock(MaybeRegBlock);
5331 
5332  // Integer arguments may need to correct register alignment (for example a
5333  // "struct { __int128 a; };" gets passed in x_2N, x_{2N+1}). In this case we
5334  // align __gr_offs to calculate the potential address.
5335  if (!IsFPR && !IsIndirect && TyAlign.getQuantity() > 8) {
5336  int Align = TyAlign.getQuantity();
5337 
5338  reg_offs = CGF.Builder.CreateAdd(
5339  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, Align - 1),
5340  "align_regoffs");
5341  reg_offs = CGF.Builder.CreateAnd(
5342  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, -Align),
5343  "aligned_regoffs");
5344  }
5345 
5346  // Update the gr_offs/vr_offs pointer for next call to va_arg on this va_list.
5347  // The fact that this is done unconditionally reflects the fact that
5348  // allocating an argument to the stack also uses up all the remaining
5349  // registers of the appropriate kind.
5350  llvm::Value *NewOffset = nullptr;
5351  NewOffset = CGF.Builder.CreateAdd(
5352  reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
5353  CGF.Builder.CreateStore(NewOffset, reg_offs_p);
5354 
5355  // Now we're in a position to decide whether this argument really was in
5356  // registers or not.
5357  llvm::Value *InRegs = nullptr;
5358  InRegs = CGF.Builder.CreateICmpSLE(
5359  NewOffset, llvm::ConstantInt::get(CGF.Int32Ty, 0), "inreg");
5360 
5361  CGF.Builder.CreateCondBr(InRegs, InRegBlock, OnStackBlock);
5362 
5363  //=======================================
5364  // Argument was in registers
5365  //=======================================
5366 
5367  // Now we emit the code for if the argument was originally passed in
5368  // registers. First start the appropriate block:
5369  CGF.EmitBlock(InRegBlock);
5370 
5371  llvm::Value *reg_top = nullptr;
5372  Address reg_top_p = CGF.Builder.CreateStructGEP(VAListAddr, reg_top_index,
5373  reg_top_offset, "reg_top_p");
5374  reg_top = CGF.Builder.CreateLoad(reg_top_p, "reg_top");
5375  Address BaseAddr(CGF.Builder.CreateInBoundsGEP(reg_top, reg_offs),
5376  CharUnits::fromQuantity(IsFPR ? 16 : 8));
5377  Address RegAddr = Address::invalid();
5378  llvm::Type *MemTy = CGF.ConvertTypeForMem(Ty);
5379 
5380  if (IsIndirect) {
5381  // If it's been passed indirectly (actually a struct), whatever we find from
5382  // stored registers or on the stack will actually be a struct **.
5383  MemTy = llvm::PointerType::getUnqual(MemTy);
5384  }
5385 
5386  const Type *Base = nullptr;
5387  uint64_t NumMembers = 0;
5388  bool IsHFA = isHomogeneousAggregate(Ty, Base, NumMembers);
5389  if (IsHFA && NumMembers > 1) {
5390  // Homogeneous aggregates passed in registers will have their elements split
5391  // and stored 16-bytes apart regardless of size (they're notionally in qN,
5392  // qN+1, ...). We reload and store into a temporary local variable
5393  // contiguously.
5394  assert(!IsIndirect && "Homogeneous aggregates should be passed directly");
5395  auto BaseTyInfo = getContext().getTypeInfoInChars(QualType(Base, 0));
5396  llvm::Type *BaseTy = CGF.ConvertType(QualType(Base, 0));
5397  llvm::Type *HFATy = llvm::ArrayType::get(BaseTy, NumMembers);
5398  Address Tmp = CGF.CreateTempAlloca(HFATy,
5399  std::max(TyAlign, BaseTyInfo.second));
5400 
5401  // On big-endian platforms, the value will be right-aligned in its slot.
5402  int Offset = 0;
5403  if (CGF.CGM.getDataLayout().isBigEndian() &&
5404  BaseTyInfo.first.getQuantity() < 16)
5405  Offset = 16 - BaseTyInfo.first.getQuantity();
5406 
5407  for (unsigned i = 0; i < NumMembers; ++i) {
5408  CharUnits BaseOffset = CharUnits::fromQuantity(16 * i + Offset);
5409  Address LoadAddr =
5410  CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, BaseOffset);
5411  LoadAddr = CGF.Builder.CreateElementBitCast(LoadAddr, BaseTy);
5412 
5413  Address StoreAddr =
5414  CGF.Builder.CreateConstArrayGEP(Tmp, i, BaseTyInfo.first);
5415 
5416  llvm::Value *Elem = CGF.Builder.CreateLoad(LoadAddr);
5417  CGF.Builder.CreateStore(Elem, StoreAddr);
5418  }
5419 
5420  RegAddr = CGF.Builder.CreateElementBitCast(Tmp, MemTy);
5421  } else {
5422  // Otherwise the object is contiguous in memory.
5423 
5424  // It might be right-aligned in its slot.
5425  CharUnits SlotSize = BaseAddr.getAlignment();
5426  if (CGF.CGM.getDataLayout().isBigEndian() && !IsIndirect &&
5427  (IsHFA || !isAggregateTypeForABI(Ty)) &&
5428  TyInfo.first < SlotSize) {
5429  CharUnits Offset = SlotSize - TyInfo.first;
5430  BaseAddr = CGF.Builder.CreateConstInBoundsByteGEP(BaseAddr, Offset);
5431  }
5432 
5433  RegAddr = CGF.Builder.CreateElementBitCast(BaseAddr, MemTy);
5434  }
5435 
5436  CGF.EmitBranch(ContBlock);
5437 
5438  //=======================================
5439  // Argument was on the stack
5440  //=======================================
5441  CGF.EmitBlock(OnStackBlock);
5442 
5443  Address stack_p = CGF.Builder.CreateStructGEP(VAListAddr, 0,
5444  CharUnits::Zero(), "stack_p");
5445  llvm::Value *OnStackPtr = CGF.Builder.CreateLoad(stack_p, "stack");
5446 
5447  // Again, stack arguments may need realignment. In this case both integer and
5448  // floating-point ones might be affected.
5449  if (!IsIndirect && TyAlign.getQuantity() > 8) {
5450  int Align = TyAlign.getQuantity();
5451 
5452  OnStackPtr = CGF.Builder.CreatePtrToInt(OnStackPtr, CGF.Int64Ty);
5453 
5454  OnStackPtr = CGF.Builder.CreateAdd(
5455  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, Align - 1),
5456  "align_stack");
5457  OnStackPtr = CGF.Builder.CreateAnd(
5458  OnStackPtr, llvm::ConstantInt::get(CGF.Int64Ty, -Align),
5459  "align_stack");
5460 
5461  OnStackPtr = CGF.Builder.CreateIntToPtr(OnStackPtr, CGF.Int8PtrTy);
5462  }
5463  Address OnStackAddr(OnStackPtr,
5464  std::max(CharUnits::fromQuantity(8), TyAlign));
5465 
5466  // All stack slots are multiples of 8 bytes.
5467  CharUnits StackSlotSize = CharUnits::fromQuantity(8);
5468  CharUnits StackSize;
5469  if (IsIndirect)
5470  StackSize = StackSlotSize;
5471  else
5472  StackSize = TyInfo.first.alignTo(StackSlotSize);
5473 
5474  llvm::Value *StackSizeC = CGF.Builder.getSize(StackSize);
5475  llvm::Value *NewStack =
5476  CGF.Builder.CreateInBoundsGEP(OnStackPtr, StackSizeC, "new_stack");
5477 
5478  // Write the new value of __stack for the next call to va_arg
5479  CGF.Builder.CreateStore(NewStack, stack_p);
5480 
5481  if (CGF.CGM.getDataLayout().isBigEndian() && !isAggregateTypeForABI(Ty) &&
5482  TyInfo.first < StackSlotSize) {
5483  CharUnits Offset = StackSlotSize - TyInfo.first;
5484  OnStackAddr = CGF.Builder.CreateConstInBoundsByteGEP(OnStackAddr, Offset);
5485  }
5486 
5487  OnStackAddr = CGF.Builder.CreateElementBitCast(OnStackAddr, MemTy);
5488 
5489  CGF.EmitBranch(ContBlock);
5490 
5491  //=======================================
5492  // Tidy up
5493  //=======================================
5494  CGF.EmitBlock(ContBlock);
5495 
5496  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
5497  OnStackAddr, OnStackBlock, "vaargs.addr");
5498 
5499  if (IsIndirect)
5500  return Address(CGF.Builder.CreateLoad(ResAddr, "vaarg.addr"),
5501  TyInfo.second);
5502 
5503  return ResAddr;
5504 }
5505 
5506 Address AArch64ABIInfo::EmitDarwinVAArg(Address VAListAddr, QualType Ty,
5507  CodeGenFunction &CGF) const {
5508  // The backend's lowering doesn't support va_arg for aggregates or
5509  // illegal vector types. Lower VAArg here for these cases and use
5510  // the LLVM va_arg instruction for everything else.
5511  if (!isAggregateTypeForABI(Ty) && !isIllegalVectorType(Ty))
5512  return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect());
5513 
5514  CharUnits SlotSize = CharUnits::fromQuantity(8);
5515 
5516  // Empty records are ignored for parameter passing purposes.
5517  if (isEmptyRecord(getContext(), Ty, true)) {
5518  Address Addr(CGF.Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
5519  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
5520  return Addr;
5521  }
5522 
5523  // The size of the actual thing passed, which might end up just
5524  // being a pointer for indirect types.
5525  auto TyInfo = getContext().getTypeInfoInChars(Ty);
5526 
5527  // Arguments bigger than 16 bytes which aren't homogeneous
5528  // aggregates should be passed indirectly.
5529  bool IsIndirect = false;
5530  if (TyInfo.first.getQuantity() > 16) {
5531  const Type *Base = nullptr;
5532  uint64_t Members = 0;
5533  IsIndirect = !isHomogeneousAggregate(Ty, Base, Members);
5534  }
5535 
5536  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect,
5537  TyInfo, SlotSize, /*AllowHigherAlign*/ true);
5538 }
5539 
5540 Address AArch64ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr,
5541  QualType Ty) const {
5542  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
5543  CGF.getContext().getTypeInfoInChars(Ty),
5545  /*allowHigherAlign*/ false);
5546 }
5547 
5548 //===----------------------------------------------------------------------===//
5549 // ARM ABI Implementation
5550 //===----------------------------------------------------------------------===//
5551 
5552 namespace {
5553 
5554 class ARMABIInfo : public SwiftABIInfo {
5555 public:
5556  enum ABIKind {
5557  APCS = 0,
5558  AAPCS = 1,
5559  AAPCS_VFP = 2,
5560  AAPCS16_VFP = 3,
5561  };
5562 
5563 private:
5564  ABIKind Kind;
5565 
5566 public:
5567  ARMABIInfo(CodeGenTypes &CGT, ABIKind _Kind)
5568  : SwiftABIInfo(CGT), Kind(_Kind) {
5569  setCCs();
5570  }
5571 
5572  bool isEABI() const {
5573  switch (getTarget().getTriple().getEnvironment()) {
5574  case llvm::Triple::Android:
5575  case llvm::Triple::EABI:
5576  case llvm::Triple::EABIHF:
5577  case llvm::Triple::GNUEABI:
5578  case llvm::Triple::GNUEABIHF:
5579  case llvm::Triple::MuslEABI:
5580  case llvm::Triple::MuslEABIHF:
5581  return true;
5582  default:
5583  return false;
5584  }
5585  }
5586 
5587  bool isEABIHF() const {
5588  switch (getTarget().getTriple().getEnvironment()) {
5589  case llvm::Triple::EABIHF:
5590  case llvm::Triple::GNUEABIHF:
5591  case llvm::Triple::MuslEABIHF:
5592  return true;
5593  default:
5594  return false;
5595  }
5596  }
5597 
5598  ABIKind getABIKind() const { return Kind; }
5599 
5600 private:
5601  ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
5602  ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
5603  ABIArgInfo classifyHomogeneousAggregate(QualType Ty, const Type *Base,
5604  uint64_t Members) const;
5605  ABIArgInfo coerceIllegalVector(QualType Ty) const;
5606  bool isIllegalVectorType(QualType Ty) const;
5607 
5608  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
5609  bool isHomogeneousAggregateSmallEnough(const Type *Ty,
5610  uint64_t Members) const override;
5611 
5612  void computeInfo(CGFunctionInfo &FI) const override;
5613 
5614  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
5615  QualType Ty) const override;
5616 
5617  llvm::CallingConv::ID getLLVMDefaultCC() const;
5618  llvm::CallingConv::ID getABIDefaultCC() const;
5619  void setCCs();
5620 
5621  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
5622  bool asReturnValue) const override {
5623  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
5624  }
5625  bool isSwiftErrorInRegister() const override {
5626  return true;
5627  }
5628  bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
5629  unsigned elts) const override;
5630 };
5631 
5632 class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
5633 public:
5634  ARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5635  :TargetCodeGenInfo(new ARMABIInfo(CGT, K)) {}
5636 
5637  const ARMABIInfo &getABIInfo() const {
5638  return static_cast<const ARMABIInfo&>(TargetCodeGenInfo::getABIInfo());
5639  }
5640 
5641  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
5642  return 13;
5643  }
5644 
5645  StringRef getARCRetainAutoreleasedReturnValueMarker() const override {
5646  return "mov\tr7, r7\t\t// marker for objc_retainAutoreleaseReturnValue";
5647  }
5648 
5649  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
5650  llvm::Value *Address) const override {
5651  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
5652 
5653  // 0-15 are the 16 integer registers.
5654  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 15);
5655  return false;
5656  }
5657 
5658  unsigned getSizeOfUnwindException() const override {
5659  if (getABIInfo().isEABI()) return 88;
5661  }
5662 
5663  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5664  CodeGen::CodeGenModule &CGM) const override {
5665  if (GV->isDeclaration())
5666  return;
5667  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
5668  if (!FD)
5669  return;
5670 
5671  const ARMInterruptAttr *Attr = FD->getAttr<ARMInterruptAttr>();
5672  if (!Attr)
5673  return;
5674 
5675  const char *Kind;
5676  switch (Attr->getInterrupt()) {
5677  case ARMInterruptAttr::Generic: Kind = ""; break;
5678  case ARMInterruptAttr::IRQ: Kind = "IRQ"; break;
5679  case ARMInterruptAttr::FIQ: Kind = "FIQ"; break;
5680  case ARMInterruptAttr::SWI: Kind = "SWI"; break;
5681  case ARMInterruptAttr::ABORT: Kind = "ABORT"; break;
5682  case ARMInterruptAttr::UNDEF: Kind = "UNDEF"; break;
5683  }
5684 
5685  llvm::Function *Fn = cast<llvm::Function>(GV);
5686 
5687  Fn->addFnAttr("interrupt", Kind);
5688 
5689  ARMABIInfo::ABIKind ABI = cast<ARMABIInfo>(getABIInfo()).getABIKind();
5690  if (ABI == ARMABIInfo::APCS)
5691  return;
5692 
5693  // AAPCS guarantees that sp will be 8-byte aligned on any public interface,
5694  // however this is not necessarily true on taking any interrupt. Instruct
5695  // the backend to perform a realignment as part of the function prologue.
5696  llvm::AttrBuilder B;
5697  B.addStackAlignmentAttr(8);
5698  Fn->addAttributes(llvm::AttributeList::FunctionIndex, B);
5699  }
5700 };
5701 
5702 class WindowsARMTargetCodeGenInfo : public ARMTargetCodeGenInfo {
5703 public:
5704  WindowsARMTargetCodeGenInfo(CodeGenTypes &CGT, ARMABIInfo::ABIKind K)
5705  : ARMTargetCodeGenInfo(CGT, K) {}
5706 
5707  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
5708  CodeGen::CodeGenModule &CGM) const override;
5709 
5710  void getDependentLibraryOption(llvm::StringRef Lib,
5711  llvm::SmallString<24> &Opt) const override {
5712  Opt = "/DEFAULTLIB:" + qualifyWindowsLibrary(Lib);
5713  }
5714 
5715  void getDetectMismatchOption(llvm::StringRef Name, llvm::StringRef Value,
5716  llvm::SmallString<32> &Opt) const override {
5717  Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\"";
5718  }
5719 };
5720 
5721 void WindowsARMTargetCodeGenInfo::setTargetAttributes(
5722  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
5723  ARMTargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
5724  if (GV->isDeclaration())
5725  return;
5726  addStackProbeTargetAttributes(D, GV, CGM);
5727 }
5728 }
5729 
5730 void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const {
5731  if (!::classifyReturnType(getCXXABI(), FI, *this))
5732  FI.getReturnInfo() =
5734 
5735  for (auto &I : FI.arguments())
5736  I.info = classifyArgumentType(I.type, FI.isVariadic());
5737 
5738  // Always honor user-specified calling convention.
5740  return;
5741 
5743  if (cc != llvm::CallingConv::C)
5745 }
5746 
5747 /// Return the default calling convention that LLVM will use.
5748 llvm::CallingConv::ID ARMABIInfo::getLLVMDefaultCC() const {
5749  // The default calling convention that LLVM will infer.
5750  if (isEABIHF() || getTarget().getTriple().isWatchABI())
5751  return llvm::CallingConv::ARM_AAPCS_VFP;
5752  else if (isEABI())
5753  return llvm::CallingConv::ARM_AAPCS;
5754  else
5755  return llvm::CallingConv::ARM_APCS;
5756 }
5757 
5758 /// Return the calling convention that our ABI would like us to use
5759 /// as the C calling convention.
5760 llvm::CallingConv::ID ARMABIInfo::getABIDefaultCC() const {
5761  switch (getABIKind()) {
5762  case APCS: return llvm::CallingConv::ARM_APCS;
5763  case AAPCS: return llvm::CallingConv::ARM_AAPCS;
5764  case AAPCS_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5765  case AAPCS16_VFP: return llvm::CallingConv::ARM_AAPCS_VFP;
5766  }
5767  llvm_unreachable("bad ABI kind");
5768 }
5769 
5770 void ARMABIInfo::setCCs() {
5771  assert(getRuntimeCC() == llvm::CallingConv::C);
5772 
5773  // Don't muddy up the IR with a ton of explicit annotations if
5774  // they'd just match what LLVM will infer from the triple.
5775  llvm::CallingConv::ID abiCC = getABIDefaultCC();
5776  if (abiCC != getLLVMDefaultCC())
5777  RuntimeCC = abiCC;
5778 }
5779 
5780 ABIArgInfo ARMABIInfo::coerceIllegalVector(QualType Ty) const {
5781  uint64_t Size = getContext().getTypeSize(Ty);
5782  if (Size <= 32) {
5783  llvm::Type *ResType =
5784  llvm::Type::getInt32Ty(getVMContext());
5785  return ABIArgInfo::getDirect(ResType);
5786  }
5787  if (Size == 64 || Size == 128) {
5788  llvm::Type *ResType = llvm::VectorType::get(
5789  llvm::Type::getInt32Ty(getVMContext()), Size / 32);
5790  return ABIArgInfo::getDirect(ResType);
5791  }
5792  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
5793 }
5794 
5795 ABIArgInfo ARMABIInfo::classifyHomogeneousAggregate(QualType Ty,
5796  const Type *Base,
5797  uint64_t Members) const {
5798  assert(Base && "Base class should be set for homogeneous aggregate");
5799  // Base can be a floating-point or a vector.
5800  if (const VectorType *VT = Base->getAs<VectorType>()) {
5801  // FP16 vectors should be converted to integer vectors
5802  if (!getTarget().hasLegalHalfType() &&
5803  (VT->getElementType()->isFloat16Type() ||
5804  VT->getElementType()->isHalfType())) {
5805  uint64_t Size = getContext().getTypeSize(VT);
5806  llvm::Type *NewVecTy = llvm::VectorType::get(
5807  llvm::Type::getInt32Ty(getVMContext()), Size / 32);
5808  llvm::Type *Ty = llvm::ArrayType::get(NewVecTy, Members);
5809  return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5810  }
5811  }
5812  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
5813 }
5814 
5816  bool isVariadic) const {
5817  // 6.1.2.1 The following argument types are VFP CPRCs:
5818  // A single-precision floating-point type (including promoted
5819  // half-precision types); A double-precision floating-point type;
5820  // A 64-bit or 128-bit containerized vector type; Homogeneous Aggregate
5821  // with a Base Type of a single- or double-precision floating-point type,
5822  // 64-bit containerized vectors or 128-bit containerized vectors with one
5823  // to four Elements.
5824  bool IsEffectivelyAAPCS_VFP = getABIKind() == AAPCS_VFP && !isVariadic;
5825 
5827 
5828  // Handle illegal vector types here.
5829  if (isIllegalVectorType(Ty))
5830  return coerceIllegalVector(Ty);
5831 
5832  // _Float16 and __fp16 get passed as if it were an int or float, but with
5833  // the top 16 bits unspecified. This is not done for OpenCL as it handles the
5834  // half type natively, and does not need to interwork with AAPCS code.
5835  if ((Ty->isFloat16Type() || Ty->isHalfType()) &&
5836  !getContext().getLangOpts().NativeHalfArgsAndReturns) {
5837  llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
5838  llvm::Type::getFloatTy(getVMContext()) :
5839  llvm::Type::getInt32Ty(getVMContext());
5840  return ABIArgInfo::getDirect(ResType);
5841  }
5842 
5843  if (!isAggregateTypeForABI(Ty)) {
5844  // Treat an enum type as its underlying type.
5845  if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
5846  Ty = EnumTy->getDecl()->getIntegerType();
5847  }
5848 
5850  : ABIArgInfo::getDirect());
5851  }
5852 
5855  }
5856 
5857  // Ignore empty records.
5858  if (isEmptyRecord(getContext(), Ty, true))
5859  return ABIArgInfo::getIgnore();
5860 
5861  if (IsEffectivelyAAPCS_VFP) {
5862  // Homogeneous Aggregates need to be expanded when we can fit the aggregate
5863  // into VFP registers.
5864  const Type *Base = nullptr;
5865  uint64_t Members = 0;
5866  if (isHomogeneousAggregate(Ty, Base, Members))
5867  return classifyHomogeneousAggregate(Ty, Base, Members);
5868  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
5869  // WatchOS does have homogeneous aggregates. Note that we intentionally use
5870  // this convention even for a variadic function: the backend will use GPRs
5871  // if needed.
5872  const Type *Base = nullptr;
5873  uint64_t Members = 0;
5874  if (isHomogeneousAggregate(Ty, Base, Members)) {
5875  assert(Base && Members <= 4 && "unexpected homogeneous aggregate");
5876  llvm::Type *Ty =
5877  llvm::ArrayType::get(CGT.ConvertType(QualType(Base, 0)), Members);
5878  return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
5879  }
5880  }
5881 
5882  if (getABIKind() == ARMABIInfo::AAPCS16_VFP &&
5883  getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(16)) {
5884  // WatchOS is adopting the 64-bit AAPCS rule on composite types: if they're
5885  // bigger than 128-bits, they get placed in space allocated by the caller,
5886  // and a pointer is passed.
5887  return ABIArgInfo::getIndirect(
5888  CharUnits::fromQuantity(getContext().getTypeAlign(Ty) / 8), false);
5889  }
5890 
5891  // Support byval for ARM.
5892  // The ABI alignment for APCS is 4-byte and for AAPCS at least 4-byte and at
5893  // most 8-byte. We realign the indirect argument if type alignment is bigger
5894  // than ABI alignment.
5895  uint64_t ABIAlign = 4;
5896  uint64_t TyAlign;
5897  if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
5898  getABIKind() == ARMABIInfo::AAPCS) {
5900  ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8);
5901  } else {
5902  TyAlign = getContext().getTypeAlignInChars(Ty).getQuantity();
5903  }
5904  if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) {
5905  assert(getABIKind() != ARMABIInfo::AAPCS16_VFP && "unexpected byval");
5907  /*ByVal=*/true,
5908  /*Realign=*/TyAlign > ABIAlign);
5909  }
5910 
5911  // On RenderScript, coerce Aggregates <= 64 bytes to an integer array of
5912  // same size and alignment.
5913  if (getTarget().isRenderScriptTarget()) {
5914  return coerceToIntArray(Ty, getContext(), getVMContext());
5915  }
5916 
5917  // Otherwise, pass by coercing to a structure of the appropriate size.
5918  llvm::Type* ElemTy;
5919  unsigned SizeRegs;
5920  // FIXME: Try to match the types of the arguments more accurately where
5921  // we can.
5922  if (TyAlign <= 4) {
5923  ElemTy = llvm::Type::getInt32Ty(getVMContext());
5924  SizeRegs = (getContext().getTypeSize(Ty) + 31) / 32;
5925  } else {
5926  ElemTy = llvm::Type::getInt64Ty(getVMContext());
5927  SizeRegs = (getContext().getTypeSize(Ty) + 63) / 64;
5928  }
5929 
5930  return ABIArgInfo::getDirect(llvm::ArrayType::get(ElemTy, SizeRegs));
5931 }
5932 
5933 static bool isIntegerLikeType(QualType Ty, ASTContext &Context,
5934  llvm::LLVMContext &VMContext) {
5935  // APCS, C Language Calling Conventions, Non-Simple Return Values: A structure
5936  // is called integer-like if its size is less than or equal to one word, and
5937  // the offset of each of its addressable sub-fields is zero.
5938 
5939  uint64_t Size = Context.getTypeSize(Ty);
5940 
5941  // Check that the type fits in a word.
5942  if (Size > 32)
5943  return false;
5944 
5945  // FIXME: Handle vector types!
5946  if (Ty->isVectorType())
5947  return false;
5948 
5949  // Float types are never treated as "integer like".
5950  if (Ty->isRealFloatingType())
5951  return false;
5952 
5953  // If this is a builtin or pointer type then it is ok.
5954  if (Ty->getAs<BuiltinType>() || Ty->isPointerType())
5955  return true;
5956 
5957  // Small complex integer types are "integer like".
5958  if (const ComplexType *CT = Ty->getAs<ComplexType>())
5959  return isIntegerLikeType(CT->getElementType(), Context, VMContext);
5960 
5961  // Single element and zero sized arrays should be allowed, by the definition
5962  // above, but they are not.
5963 
5964  // Otherwise, it must be a record type.
5965  const RecordType *RT = Ty->getAs<RecordType>();
5966  if (!RT) return false;
5967 
5968  // Ignore records with flexible arrays.
5969  const RecordDecl *RD = RT->getDecl();
5970  if (RD->hasFlexibleArrayMember())
5971  return false;
5972 
5973  // Check that all sub-fields are at offset 0, and are themselves "integer
5974  // like".
5975  const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
5976 
5977  bool HadField = false;
5978  unsigned idx = 0;
5979  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
5980  i != e; ++i, ++idx) {
5981  const FieldDecl *FD = *i;
5982 
5983  // Bit-fields are not addressable, we only need to verify they are "integer
5984  // like". We still have to disallow a subsequent non-bitfield, for example:
5985  // struct { int : 0; int x }
5986  // is non-integer like according to gcc.
5987  if (FD->isBitField()) {
5988  if (!RD->isUnion())
5989  HadField = true;
5990 
5991  if (!isIntegerLikeType(FD->getType(), Context, VMContext))
5992  return false;
5993 
5994  continue;
5995  }
5996 
5997  // Check if this field is at offset 0.
5998  if (Layout.getFieldOffset(idx) != 0)
5999  return false;
6000 
6001  if (!isIntegerLikeType(FD->getType(), Context, VMContext))
6002  return false;
6003 
6004  // Only allow at most one field in a structure. This doesn't match the
6005  // wording above, but follows gcc in situations with a field following an
6006  // empty structure.
6007  if (!RD->isUnion()) {
6008  if (HadField)
6009  return false;
6010 
6011  HadField = true;
6012  }
6013  }
6014 
6015  return true;
6016 }
6017 
6019  bool isVariadic) const {
6020  bool IsEffectivelyAAPCS_VFP =
6021  (getABIKind() == AAPCS_VFP || getABIKind() == AAPCS16_VFP) && !isVariadic;
6022 
6023  if (RetTy->isVoidType())
6024  return ABIArgInfo::getIgnore();
6025 
6026  if (const VectorType *VT = RetTy->getAs<VectorType>()) {
6027  // Large vector types should be returned via memory.
6028  if (getContext().getTypeSize(RetTy) > 128)
6029  return getNaturalAlignIndirect(RetTy);
6030  // FP16 vectors should be converted to integer vectors
6031  if (!getTarget().hasLegalHalfType() &&
6032  (VT->getElementType()->isFloat16Type() ||
6033  VT->getElementType()->isHalfType()))
6034  return coerceIllegalVector(RetTy);
6035  }
6036 
6037  // _Float16 and __fp16 get returned as if it were an int or float, but with
6038  // the top 16 bits unspecified. This is not done for OpenCL as it handles the
6039  // half type natively, and does not need to interwork with AAPCS code.
6040  if ((RetTy->isFloat16Type() || RetTy->isHalfType()) &&
6041  !getContext().getLangOpts().NativeHalfArgsAndReturns) {
6042  llvm::Type *ResType = IsEffectivelyAAPCS_VFP ?
6043  llvm::Type::getFloatTy(getVMContext()) :
6044  llvm::Type::getInt32Ty(getVMContext());
6045  return ABIArgInfo::getDirect(ResType);
6046  }
6047 
6048  if (!isAggregateTypeForABI(RetTy)) {
6049  // Treat an enum type as its underlying type.
6050  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6051  RetTy = EnumTy->getDecl()->getIntegerType();
6052 
6053  return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
6055  }
6056 
6057  // Are we following APCS?
6058  if (getABIKind() == APCS) {
6059  if (isEmptyRecord(getContext(), RetTy, false))
6060  return ABIArgInfo::getIgnore();
6061 
6062  // Complex types are all returned as packed integers.
6063  //
6064  // FIXME: Consider using 2 x vector types if the back end handles them
6065  // correctly.
6066  if (RetTy->isAnyComplexType())
6067  return ABIArgInfo::getDirect(llvm::IntegerType::get(
6068  getVMContext(), getContext().getTypeSize(RetTy)));
6069 
6070  // Integer like structures are returned in r0.
6071  if (isIntegerLikeType(RetTy, getContext(), getVMContext())) {
6072  // Return in the smallest viable integer type.
6073  uint64_t Size = getContext().getTypeSize(RetTy);
6074  if (Size <= 8)
6075  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6076  if (Size <= 16)
6077  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6078  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6079  }
6080 
6081  // Otherwise return in memory.
6082  return getNaturalAlignIndirect(RetTy);
6083  }
6084 
6085  // Otherwise this is an AAPCS variant.
6086 
6087  if (isEmptyRecord(getContext(), RetTy, true))
6088  return ABIArgInfo::getIgnore();
6089 
6090  // Check for homogeneous aggregates with AAPCS-VFP.
6091  if (IsEffectivelyAAPCS_VFP) {
6092  const Type *Base = nullptr;
6093  uint64_t Members = 0;
6094  if (isHomogeneousAggregate(RetTy, Base, Members))
6095  return classifyHomogeneousAggregate(RetTy, Base, Members);
6096  }
6097 
6098  // Aggregates <= 4 bytes are returned in r0; other aggregates
6099  // are returned indirectly.
6100  uint64_t Size = getContext().getTypeSize(RetTy);
6101  if (Size <= 32) {
6102  // On RenderScript, coerce Aggregates <= 4 bytes to an integer array of
6103  // same size and alignment.
6104  if (getTarget().isRenderScriptTarget()) {
6105  return coerceToIntArray(RetTy, getContext(), getVMContext());
6106  }
6107  if (getDataLayout().isBigEndian())
6108  // Return in 32 bit integer integer type (as if loaded by LDR, AAPCS 5.4)
6109  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6110 
6111  // Return in the smallest viable integer type.
6112  if (Size <= 8)
6113  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
6114  if (Size <= 16)
6115  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
6116  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
6117  } else if (Size <= 128 && getABIKind() == AAPCS16_VFP) {
6118  llvm::Type *Int32Ty = llvm::Type::getInt32Ty(getVMContext());
6119  llvm::Type *CoerceTy =
6120  llvm::ArrayType::get(Int32Ty, llvm::alignTo(Size, 32) / 32);
6121  return ABIArgInfo::getDirect(CoerceTy);
6122  }
6123 
6124  return getNaturalAlignIndirect(RetTy);
6125 }
6126 
6127 /// isIllegalVector - check whether Ty is an illegal vector type.
6128 bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
6129  if (const VectorType *VT = Ty->getAs<VectorType> ()) {
6130  // On targets that don't support FP16, FP16 is expanded into float, and we
6131  // don't want the ABI to depend on whether or not FP16 is supported in
6132  // hardware. Thus return false to coerce FP16 vectors into integer vectors.
6133  if (!getTarget().hasLegalHalfType() &&
6134  (VT->getElementType()->isFloat16Type() ||
6135  VT->getElementType()->isHalfType()))
6136  return true;
6137  if (isAndroid()) {
6138  // Android shipped using Clang 3.1, which supported a slightly different
6139  // vector ABI. The primary differences were that 3-element vector types
6140  // were legal, and so were sub 32-bit vectors (i.e. <2 x i8>). This path
6141  // accepts that legacy behavior for Android only.
6142  // Check whether VT is legal.
6143  unsigned NumElements = VT->getNumElements();
6144  // NumElements should be power of 2 or equal to 3.
6145  if (!llvm::isPowerOf2_32(NumElements) && NumElements != 3)
6146  return true;
6147  } else {
6148  // Check whether VT is legal.
6149  unsigned NumElements = VT->getNumElements();
6150  uint64_t Size = getContext().getTypeSize(VT);
6151  // NumElements should be power of 2.
6152  if (!llvm::isPowerOf2_32(NumElements))
6153  return true;
6154  // Size should be greater than 32 bits.
6155  return Size <= 32;
6156  }
6157  }
6158  return false;
6159 }
6160 
6161 bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
6162  llvm::Type *eltTy,
6163  unsigned numElts) const {
6164  if (!llvm::isPowerOf2_32(numElts))
6165  return false;
6166  unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
6167  if (size > 64)
6168  return false;
6169  if (vectorSize.getQuantity() != 8 &&
6170  (vectorSize.getQuantity() != 16 || numElts == 1))
6171  return false;
6172  return true;
6173 }
6174 
6175 bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
6176  // Homogeneous aggregates for AAPCS-VFP must have base types of float,
6177  // double, or 64-bit or 128-bit vectors.
6178  if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
6179  if (BT->getKind() == BuiltinType::Float ||
6180  BT->getKind() == BuiltinType::Double ||
6181  BT->getKind() == BuiltinType::LongDouble)
6182  return true;
6183  } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
6184  unsigned VecSize = getContext().getTypeSize(VT);
6185  if (VecSize == 64 || VecSize == 128)
6186  return true;
6187  }
6188  return false;
6189 }
6190 
6191 bool ARMABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base,
6192  uint64_t Members) const {
6193  return Members <= 4;
6194 }
6195 
6196 Address ARMABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6197  QualType Ty) const {
6198  CharUnits SlotSize = CharUnits::fromQuantity(4);
6199 
6200  // Empty records are ignored for parameter passing purposes.
6201  if (isEmptyRecord(getContext(), Ty, true)) {
6202  Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
6203  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
6204  return Addr;
6205  }
6206 
6207  auto TyInfo = getContext().getTypeInfoInChars(Ty);
6208  CharUnits TyAlignForABI = TyInfo.second;
6209 
6210  // Use indirect if size of the illegal vector is bigger than 16 bytes.
6211  bool IsIndirect = false;
6212  const Type *Base = nullptr;
6213  uint64_t Members = 0;
6214  if (TyInfo.first > CharUnits::fromQuantity(16) && isIllegalVectorType(Ty)) {
6215  IsIndirect = true;
6216 
6217  // ARMv7k passes structs bigger than 16 bytes indirectly, in space
6218  // allocated by the caller.
6219  } else if (TyInfo.first > CharUnits::fromQuantity(16) &&
6220  getABIKind() == ARMABIInfo::AAPCS16_VFP &&
6221  !isHomogeneousAggregate(Ty, Base, Members)) {
6222  IsIndirect = true;
6223 
6224  // Otherwise, bound the type's ABI alignment.
6225  // The ABI alignment for 64-bit or 128-bit vectors is 8 for AAPCS and 4 for
6226  // APCS. For AAPCS, the ABI alignment is at least 4-byte and at most 8-byte.
6227  // Our callers should be prepared to handle an under-aligned address.
6228  } else if (getABIKind() == ARMABIInfo::AAPCS_VFP ||
6229  getABIKind() == ARMABIInfo::AAPCS) {
6230  TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6231  TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(8));
6232  } else if (getABIKind() == ARMABIInfo::AAPCS16_VFP) {
6233  // ARMv7k allows type alignment up to 16 bytes.
6234  TyAlignForABI = std::max(TyAlignForABI, CharUnits::fromQuantity(4));
6235  TyAlignForABI = std::min(TyAlignForABI, CharUnits::fromQuantity(16));
6236  } else {
6237  TyAlignForABI = CharUnits::fromQuantity(4);
6238  }
6239  TyInfo.second = TyAlignForABI;
6240 
6241  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TyInfo,
6242  SlotSize, /*AllowHigherAlign*/ true);
6243 }
6244 
6245 //===----------------------------------------------------------------------===//
6246 // NVPTX ABI Implementation
6247 //===----------------------------------------------------------------------===//
6248 
6249 namespace {
6250 
6251 class NVPTXABIInfo : public ABIInfo {
6252 public:
6253  NVPTXABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
6254 
6255  ABIArgInfo classifyReturnType(QualType RetTy) const;
6257 
6258  void computeInfo(CGFunctionInfo &FI) const override;
6259  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6260  QualType Ty) const override;
6261 };
6262 
6263 class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
6264 public:
6265  NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
6266  : TargetCodeGenInfo(new NVPTXABIInfo(CGT)) {}
6267 
6268  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6269  CodeGen::CodeGenModule &M) const override;
6270  bool shouldEmitStaticExternCAliases() const override;
6271 
6272 private:
6273  // Adds a NamedMDNode with F, Name, and Operand as operands, and adds the
6274  // resulting MDNode to the nvvm.annotations MDNode.
6275  static void addNVVMMetadata(llvm::Function *F, StringRef Name, int Operand);
6276 };
6277 
6279  if (RetTy->isVoidType())
6280  return ABIArgInfo::getIgnore();
6281 
6282  // note: this is different from default ABI
6283  if (!RetTy->isScalarType())
6284  return ABIArgInfo::getDirect();
6285 
6286  // Treat an enum type as its underlying type.
6287  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
6288  RetTy = EnumTy->getDecl()->getIntegerType();
6289 
6290  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
6291  : ABIArgInfo::getDirect());
6292 }
6293 
6295  // Treat an enum type as its underlying type.
6296  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6297  Ty = EnumTy->getDecl()->getIntegerType();
6298 
6299  // Return aggregates type as indirect by value
6300  if (isAggregateTypeForABI(Ty))
6301  return getNaturalAlignIndirect(Ty, /* byval */ true);
6302 
6304  : ABIArgInfo::getDirect());
6305 }
6306 
6307 void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
6308  if (!getCXXABI().classifyReturnType(FI))
6310  for (auto &I : FI.arguments())
6311  I.info = classifyArgumentType(I.type);
6312 
6313  // Always honor user-specified calling convention.
6315  return;
6316 
6318 }
6319 
6320 Address NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6321  QualType Ty) const {
6322  llvm_unreachable("NVPTX does not support varargs");
6323 }
6324 
6325 void NVPTXTargetCodeGenInfo::setTargetAttributes(
6326  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6327  if (GV->isDeclaration())
6328  return;
6329  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6330  if (!FD) return;
6331 
6332  llvm::Function *F = cast<llvm::Function>(GV);
6333 
6334  // Perform special handling in OpenCL mode
6335  if (M.getLangOpts().OpenCL) {
6336  // Use OpenCL function attributes to check for kernel functions
6337  // By default, all functions are device functions
6338  if (FD->hasAttr<OpenCLKernelAttr>()) {
6339  // OpenCL __kernel functions get kernel metadata
6340  // Create !{<func-ref>, metadata !"kernel", i32 1} node
6341  addNVVMMetadata(F, "kernel", 1);
6342  // And kernel functions are not subject to inlining
6343  F->addFnAttr(llvm::Attribute::NoInline);
6344  }
6345  }
6346 
6347  // Perform special handling in CUDA mode.
6348  if (M.getLangOpts().CUDA) {
6349  // CUDA __global__ functions get a kernel metadata entry. Since
6350  // __global__ functions cannot be called from the device, we do not
6351  // need to set the noinline attribute.
6352  if (FD->hasAttr<CUDAGlobalAttr>()) {
6353  // Create !{<func-ref>, metadata !"kernel", i32 1} node
6354  addNVVMMetadata(F, "kernel", 1);
6355  }
6356  if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>()) {
6357  // Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
6358  llvm::APSInt MaxThreads(32);
6359  MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(M.getContext());
6360  if (MaxThreads > 0)
6361  addNVVMMetadata(F, "maxntidx", MaxThreads.getExtValue());
6362 
6363  // min blocks is an optional argument for CUDALaunchBoundsAttr. If it was
6364  // not specified in __launch_bounds__ or if the user specified a 0 value,
6365  // we don't have to add a PTX directive.
6366  if (Attr->getMinBlocks()) {
6367  llvm::APSInt MinBlocks(32);
6368  MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(M.getContext());
6369  if (MinBlocks > 0)
6370  // Create !{<func-ref>, metadata !"minctasm", i32 <val>} node
6371  addNVVMMetadata(F, "minctasm", MinBlocks.getExtValue());
6372  }
6373  }
6374  }
6375 }
6376 
6377 void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::Function *F, StringRef Name,
6378  int Operand) {
6379  llvm::Module *M = F->getParent();
6380  llvm::LLVMContext &Ctx = M->getContext();
6381 
6382  // Get "nvvm.annotations" metadata node
6383  llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
6384 
6385  llvm::Metadata *MDVals[] = {
6386  llvm::ConstantAsMetadata::get(F), llvm::MDString::get(Ctx, Name),
6387  llvm::ConstantAsMetadata::get(
6388  llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
6389  // Append metadata to nvvm.annotations
6390  MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
6391 }
6392 
6393 bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
6394  return false;
6395 }
6396 }
6397 
6398 //===----------------------------------------------------------------------===//
6399 // SystemZ ABI Implementation
6400 //===----------------------------------------------------------------------===//
6401 
6402 namespace {
6403 
6404 class SystemZABIInfo : public SwiftABIInfo {
6405  bool HasVector;
6406 
6407 public:
6408  SystemZABIInfo(CodeGenTypes &CGT, bool HV)
6409  : SwiftABIInfo(CGT), HasVector(HV) {}
6410 
6411  bool isPromotableIntegerType(QualType Ty) const;
6412  bool isCompoundType(QualType Ty) const;
6413  bool isVectorArgumentType(QualType Ty) const;
6414  bool isFPArgumentType(QualType Ty) const;
6415  QualType GetSingleElementType(QualType Ty) const;
6416 
6417  ABIArgInfo classifyReturnType(QualType RetTy) const;
6419 
6420  void computeInfo(CGFunctionInfo &FI) const override {
6421  if (!getCXXABI().classifyReturnType(FI))
6423  for (auto &I : FI.arguments())
6424  I.info = classifyArgumentType(I.type);
6425  }
6426 
6427  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6428  QualType Ty) const override;
6429 
6430  bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars,
6431  bool asReturnValue) const override {
6432  return occupiesMoreThan(CGT, scalars, /*total*/ 4);
6433  }
6434  bool isSwiftErrorInRegister() const override {
6435  return false;
6436  }
6437 };
6438 
6439 class SystemZTargetCodeGenInfo : public TargetCodeGenInfo {
6440 public:
6441  SystemZTargetCodeGenInfo(CodeGenTypes &CGT, bool HasVector)
6442  : TargetCodeGenInfo(new SystemZABIInfo(CGT, HasVector)) {}
6443 };
6444 
6445 }
6446 
6447 bool SystemZABIInfo::isPromotableIntegerType(QualType Ty) const {
6448  // Treat an enum type as its underlying type.
6449  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
6450  Ty = EnumTy->getDecl()->getIntegerType();
6451 
6452  // Promotable integer types are required to be promoted by the ABI.
6453  if (Ty->isPromotableIntegerType())
6454  return true;
6455 
6456  // 32-bit values must also be promoted.
6457  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6458  switch (BT->getKind()) {
6459  case BuiltinType::Int:
6460  case BuiltinType::UInt:
6461  return true;
6462  default:
6463  return false;
6464  }
6465  return false;
6466 }
6467 
6468 bool SystemZABIInfo::isCompoundType(QualType Ty) const {
6469  return (Ty->isAnyComplexType() ||
6470  Ty->isVectorType() ||
6471  isAggregateTypeForABI(Ty));
6472 }
6473 
6474 bool SystemZABIInfo::isVectorArgumentType(QualType Ty) const {
6475  return (HasVector &&
6476  Ty->isVectorType() &&
6477  getContext().getTypeSize(Ty) <= 128);
6478 }
6479 
6480 bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
6481  if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
6482  switch (BT->getKind()) {
6483  case BuiltinType::Float:
6484  case BuiltinType::Double:
6485  return true;
6486  default:
6487  return false;
6488  }
6489 
6490  return false;
6491 }
6492 
6493 QualType SystemZABIInfo::GetSingleElementType(QualType Ty) const {
6494  if (const RecordType *RT = Ty->getAsStructureType()) {
6495  const RecordDecl *RD = RT->getDecl();
6496  QualType Found;
6497 
6498  // If this is a C++ record, check the bases first.
6499  if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
6500  for (const auto &I : CXXRD->bases()) {
6501  QualType Base = I.getType();
6502 
6503  // Empty bases don't affect things either way.
6504  if (isEmptyRecord(getContext(), Base, true))
6505  continue;
6506 
6507  if (!Found.isNull())
6508  return Ty;
6509  Found = GetSingleElementType(Base);
6510  }
6511 
6512  // Check the fields.
6513  for (const auto *FD : RD->fields()) {
6514  // For compatibility with GCC, ignore empty bitfields in C++ mode.
6515  // Unlike isSingleElementStruct(), empty structure and array fields
6516  // do count. So do anonymous bitfields that aren't zero-sized.
6517  if (getContext().getLangOpts().CPlusPlus &&
6518  FD->isZeroLengthBitField(getContext()))
6519  continue;
6520 
6521  // Unlike isSingleElementStruct(), arrays do not count.
6522  // Nested structures still do though.
6523  if (!Found.isNull())
6524  return Ty;
6525  Found = GetSingleElementType(FD->getType());
6526  }
6527 
6528  // Unlike isSingleElementStruct(), trailing padding is allowed.
6529  // An 8-byte aligned struct s { float f; } is passed as a double.
6530  if (!Found.isNull())
6531  return Found;
6532  }
6533 
6534  return Ty;
6535 }
6536 
6537 Address SystemZABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6538  QualType Ty) const {
6539  // Assume that va_list type is correct; should be pointer to LLVM type:
6540  // struct {
6541  // i64 __gpr;
6542  // i64 __fpr;
6543  // i8 *__overflow_arg_area;
6544  // i8 *__reg_save_area;
6545  // };
6546 
6547  // Every non-vector argument occupies 8 bytes and is passed by preference
6548  // in either GPRs or FPRs. Vector arguments occupy 8 or 16 bytes and are
6549  // always passed on the stack.
6550  Ty = getContext().getCanonicalType(Ty);
6551  auto TyInfo = getContext().getTypeInfoInChars(Ty);
6552  llvm::Type *ArgTy = CGF.ConvertTypeForMem(Ty);
6553  llvm::Type *DirectTy = ArgTy;
6555  bool IsIndirect = AI.isIndirect();
6556  bool InFPRs = false;
6557  bool IsVector = false;
6558  CharUnits UnpaddedSize;
6559  CharUnits DirectAlign;
6560  if (IsIndirect) {
6561  DirectTy = llvm::PointerType::getUnqual(DirectTy);
6562  UnpaddedSize = DirectAlign = CharUnits::fromQuantity(8);
6563  } else {
6564  if (AI.getCoerceToType())
6565  ArgTy = AI.getCoerceToType();
6566  InFPRs = ArgTy->isFloatTy() || ArgTy->isDoubleTy();
6567  IsVector = ArgTy->isVectorTy();
6568  UnpaddedSize = TyInfo.first;
6569  DirectAlign = TyInfo.second;
6570  }
6571  CharUnits PaddedSize = CharUnits::fromQuantity(8);
6572  if (IsVector && UnpaddedSize > PaddedSize)
6573  PaddedSize = CharUnits::fromQuantity(16);
6574  assert((UnpaddedSize <= PaddedSize) && "Invalid argument size.");
6575 
6576  CharUnits Padding = (PaddedSize - UnpaddedSize);
6577 
6578  llvm::Type *IndexTy = CGF.Int64Ty;
6579  llvm::Value *PaddedSizeV =
6580  llvm::ConstantInt::get(IndexTy, PaddedSize.getQuantity());
6581 
6582  if (IsVector) {
6583  // Work out the address of a vector argument on the stack.
6584  // Vector arguments are always passed in the high bits of a
6585  // single (8 byte) or double (16 byte) stack slot.
6586  Address OverflowArgAreaPtr =
6587  CGF.Builder.CreateStructGEP(VAListAddr, 2, CharUnits::fromQuantity(16),
6588  "overflow_arg_area_ptr");
6589  Address OverflowArgArea =
6590  Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6591  TyInfo.second);
6592  Address MemAddr =
6593  CGF.Builder.CreateElementBitCast(OverflowArgArea, DirectTy, "mem_addr");
6594 
6595  // Update overflow_arg_area_ptr pointer
6596  llvm::Value *NewOverflowArgArea =
6597  CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6598  "overflow_arg_area");
6599  CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6600 
6601  return MemAddr;
6602  }
6603 
6604  assert(PaddedSize.getQuantity() == 8);
6605 
6606  unsigned MaxRegs, RegCountField, RegSaveIndex;
6607  CharUnits RegPadding;
6608  if (InFPRs) {
6609  MaxRegs = 4; // Maximum of 4 FPR arguments
6610  RegCountField = 1; // __fpr
6611  RegSaveIndex = 16; // save offset for f0
6612  RegPadding = CharUnits(); // floats are passed in the high bits of an FPR
6613  } else {
6614  MaxRegs = 5; // Maximum of 5 GPR arguments
6615  RegCountField = 0; // __gpr
6616  RegSaveIndex = 2; // save offset for r2
6617  RegPadding = Padding; // values are passed in the low bits of a GPR
6618  }
6619 
6620  Address RegCountPtr = CGF.Builder.CreateStructGEP(
6621  VAListAddr, RegCountField, RegCountField * CharUnits::fromQuantity(8),
6622  "reg_count_ptr");
6623  llvm::Value *RegCount = CGF.Builder.CreateLoad(RegCountPtr, "reg_count");
6624  llvm::Value *MaxRegsV = llvm::ConstantInt::get(IndexTy, MaxRegs);
6625  llvm::Value *InRegs = CGF.Builder.CreateICmpULT(RegCount, MaxRegsV,
6626  "fits_in_regs");
6627 
6628  llvm::BasicBlock *InRegBlock = CGF.createBasicBlock("vaarg.in_reg");
6629  llvm::BasicBlock *InMemBlock = CGF.createBasicBlock("vaarg.in_mem");
6630  llvm::BasicBlock *ContBlock = CGF.createBasicBlock("vaarg.end");
6631  CGF.Builder.CreateCondBr(InRegs, InRegBlock, InMemBlock);
6632 
6633  // Emit code to load the value if it was passed in registers.
6634  CGF.EmitBlock(InRegBlock);
6635 
6636  // Work out the address of an argument register.
6637  llvm::Value *ScaledRegCount =
6638  CGF.Builder.CreateMul(RegCount, PaddedSizeV, "scaled_reg_count");
6639  llvm::Value *RegBase =
6640  llvm::ConstantInt::get(IndexTy, RegSaveIndex * PaddedSize.getQuantity()
6641  + RegPadding.getQuantity());
6642  llvm::Value *RegOffset =
6643  CGF.Builder.CreateAdd(ScaledRegCount, RegBase, "reg_offset");
6644  Address RegSaveAreaPtr =
6645  CGF.Builder.CreateStructGEP(VAListAddr, 3, CharUnits::fromQuantity(24),
6646  "reg_save_area_ptr");
6647  llvm::Value *RegSaveArea =
6648  CGF.Builder.CreateLoad(RegSaveAreaPtr, "reg_save_area");
6649  Address RawRegAddr(CGF.Builder.CreateGEP(RegSaveArea, RegOffset,
6650  "raw_reg_addr"),
6651  PaddedSize);
6652  Address RegAddr =
6653  CGF.Builder.CreateElementBitCast(RawRegAddr, DirectTy, "reg_addr");
6654 
6655  // Update the register count
6656  llvm::Value *One = llvm::ConstantInt::get(IndexTy, 1);
6657  llvm::Value *NewRegCount =
6658  CGF.Builder.CreateAdd(RegCount, One, "reg_count");
6659  CGF.Builder.CreateStore(NewRegCount, RegCountPtr);
6660  CGF.EmitBranch(ContBlock);
6661 
6662  // Emit code to load the value if it was passed in memory.
6663  CGF.EmitBlock(InMemBlock);
6664 
6665  // Work out the address of a stack argument.
6666  Address OverflowArgAreaPtr = CGF.Builder.CreateStructGEP(
6667  VAListAddr, 2, CharUnits::fromQuantity(16), "overflow_arg_area_ptr");
6668  Address OverflowArgArea =
6669  Address(CGF.Builder.CreateLoad(OverflowArgAreaPtr, "overflow_arg_area"),
6670  PaddedSize);
6671  Address RawMemAddr =
6672  CGF.Builder.CreateConstByteGEP(OverflowArgArea, Padding, "raw_mem_addr");
6673  Address MemAddr =
6674  CGF.Builder.CreateElementBitCast(RawMemAddr, DirectTy, "mem_addr");
6675 
6676  // Update overflow_arg_area_ptr pointer
6677  llvm::Value *NewOverflowArgArea =
6678  CGF.Builder.CreateGEP(OverflowArgArea.getPointer(), PaddedSizeV,
6679  "overflow_arg_area");
6680  CGF.Builder.CreateStore(NewOverflowArgArea, OverflowArgAreaPtr);
6681  CGF.EmitBranch(ContBlock);
6682 
6683  // Return the appropriate result.
6684  CGF.EmitBlock(ContBlock);
6685  Address ResAddr = emitMergePHI(CGF, RegAddr, InRegBlock,
6686  MemAddr, InMemBlock, "va_arg.addr");
6687 
6688  if (IsIndirect)
6689  ResAddr = Address(CGF.Builder.CreateLoad(ResAddr, "indirect_arg"),
6690  TyInfo.second);
6691 
6692  return ResAddr;
6693 }
6694 
6696  if (RetTy->isVoidType())
6697  return ABIArgInfo::getIgnore();
6698  if (isVectorArgumentType(RetTy))
6699  return ABIArgInfo::getDirect();
6700  if (isCompoundType(RetTy) || getContext().getTypeSize(RetTy) > 64)
6701  return getNaturalAlignIndirect(RetTy);
6702  return (isPromotableIntegerType(RetTy) ? ABIArgInfo::getExtend(RetTy)
6703  : ABIArgInfo::getDirect());
6704 }
6705 
6707  // Handle the generic C++ ABI.
6710 
6711  // Integers and enums are extended to full register width.
6712  if (isPromotableIntegerType(Ty))
6713  return ABIArgInfo::getExtend(Ty);
6714 
6715  // Handle vector types and vector-like structure types. Note that
6716  // as opposed to float-like structure types, we do not allow any
6717  // padding for vector-like structures, so verify the sizes match.
6718  uint64_t Size = getContext().getTypeSize(Ty);
6719  QualType SingleElementTy = GetSingleElementType(Ty);
6720  if (isVectorArgumentType(SingleElementTy) &&
6721  getContext().getTypeSize(SingleElementTy) == Size)
6722  return ABIArgInfo::getDirect(CGT.ConvertType(SingleElementTy));
6723 
6724  // Values that are not 1, 2, 4 or 8 bytes in size are passed indirectly.
6725  if (Size != 8 && Size != 16 && Size != 32 && Size != 64)
6726  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6727 
6728  // Handle small structures.
6729  if (const RecordType *RT = Ty->getAs<RecordType>()) {
6730  // Structures with flexible arrays have variable length, so really
6731  // fail the size test above.
6732  const RecordDecl *RD = RT->getDecl();
6733  if (RD->hasFlexibleArrayMember())
6734  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6735 
6736  // The structure is passed as an unextended integer, a float, or a double.
6737  llvm::Type *PassTy;
6738  if (isFPArgumentType(SingleElementTy)) {
6739  assert(Size == 32 || Size == 64);
6740  if (Size == 32)
6741  PassTy = llvm::Type::getFloatTy(getVMContext());
6742  else
6743  PassTy = llvm::Type::getDoubleTy(getVMContext());
6744  } else
6745  PassTy = llvm::IntegerType::get(getVMContext(), Size);
6746  return ABIArgInfo::getDirect(PassTy);
6747  }
6748 
6749  // Non-structure compounds are passed indirectly.
6750  if (isCompoundType(Ty))
6751  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
6752 
6753  return ABIArgInfo::getDirect(nullptr);
6754 }
6755 
6756 //===----------------------------------------------------------------------===//
6757 // MSP430 ABI Implementation
6758 //===----------------------------------------------------------------------===//
6759 
6760 namespace {
6761 
6762 class MSP430TargetCodeGenInfo : public TargetCodeGenInfo {
6763 public:
6764  MSP430TargetCodeGenInfo(CodeGenTypes &CGT)
6765  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
6766  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6767  CodeGen::CodeGenModule &M) const override;
6768 };
6769 
6770 }
6771 
6772 void MSP430TargetCodeGenInfo::setTargetAttributes(
6773  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
6774  if (GV->isDeclaration())
6775  return;
6776  if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
6777  const auto *InterruptAttr = FD->getAttr<MSP430InterruptAttr>();
6778  if (!InterruptAttr)
6779  return;
6780 
6781  // Handle 'interrupt' attribute:
6782  llvm::Function *F = cast<llvm::Function>(GV);
6783 
6784  // Step 1: Set ISR calling convention.
6785  F->setCallingConv(llvm::CallingConv::MSP430_INTR);
6786 
6787  // Step 2: Add attributes goodness.
6788  F->addFnAttr(llvm::Attribute::NoInline);
6789  F->addFnAttr("interrupt", llvm::utostr(InterruptAttr->getNumber()));
6790  }
6791 }
6792 
6793 //===----------------------------------------------------------------------===//
6794 // MIPS ABI Implementation. This works for both little-endian and
6795 // big-endian variants.
6796 //===----------------------------------------------------------------------===//
6797 
6798 namespace {
6799 class MipsABIInfo : public ABIInfo {
6800  bool IsO32;
6801  unsigned MinABIStackAlignInBytes, StackAlignInBytes;
6802  void CoerceToIntArgs(uint64_t TySize,
6803  SmallVectorImpl<llvm::Type *> &ArgList) const;
6804  llvm::Type* HandleAggregates(QualType Ty, uint64_t TySize) const;
6805  llvm::Type* returnAggregateInRegs(QualType RetTy, uint64_t Size) const;
6806  llvm::Type* getPaddingType(uint64_t Align, uint64_t Offset) const;
6807 public:
6808  MipsABIInfo(CodeGenTypes &CGT, bool _IsO32) :
6809  ABIInfo(CGT), IsO32(_IsO32), MinABIStackAlignInBytes(IsO32 ? 4 : 8),
6810  StackAlignInBytes(IsO32 ? 8 : 16) {}
6811 
6812  ABIArgInfo classifyReturnType(QualType RetTy) const;
6813  ABIArgInfo classifyArgumentType(QualType RetTy, uint64_t &Offset) const;
6814  void computeInfo(CGFunctionInfo &FI) const override;
6815  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
6816  QualType Ty) const override;
6817  ABIArgInfo extendType(QualType Ty) const;
6818 };
6819 
6820 class MIPSTargetCodeGenInfo : public TargetCodeGenInfo {
6821  unsigned SizeOfUnwindException;
6822 public:
6823  MIPSTargetCodeGenInfo(CodeGenTypes &CGT, bool IsO32)
6824  : TargetCodeGenInfo(new MipsABIInfo(CGT, IsO32)),
6825  SizeOfUnwindException(IsO32 ? 24 : 32) {}
6826 
6827  int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override {
6828  return 29;
6829  }
6830 
6831  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
6832  CodeGen::CodeGenModule &CGM) const override {
6833  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
6834  if (!FD) return;
6835  llvm::Function *Fn = cast<llvm::Function>(GV);
6836 
6837  if (FD->hasAttr<MipsLongCallAttr>())
6838  Fn->addFnAttr("long-call");
6839  else if (FD->hasAttr<MipsShortCallAttr>())
6840  Fn->addFnAttr("short-call");
6841 
6842  // Other attributes do not have a meaning for declarations.
6843  if (GV->isDeclaration())
6844  return;
6845 
6846  if (FD->hasAttr<Mips16Attr>()) {
6847  Fn->addFnAttr("mips16");
6848  }
6849  else if (FD->hasAttr<NoMips16Attr>()) {
6850  Fn->addFnAttr("nomips16");
6851  }
6852 
6853  if (FD->hasAttr<MicroMipsAttr>())
6854  Fn->addFnAttr("micromips");
6855  else if (FD->hasAttr<NoMicroMipsAttr>())
6856  Fn->addFnAttr("nomicromips");
6857 
6858  const MipsInterruptAttr *Attr = FD->getAttr<MipsInterruptAttr>();
6859  if (!Attr)
6860  return;
6861 
6862  const char *Kind;
6863  switch (Attr->getInterrupt()) {
6864  case MipsInterruptAttr::eic: Kind = "eic"; break;
6865  case MipsInterruptAttr::sw0: Kind = "sw0"; break;
6866  case MipsInterruptAttr::sw1: Kind = "sw1"; break;
6867  case MipsInterruptAttr::hw0: Kind = "hw0"; break;
6868  case MipsInterruptAttr::hw1: Kind = "hw1"; break;
6869  case MipsInterruptAttr::hw2: Kind = "hw2"; break;
6870  case MipsInterruptAttr::hw3: Kind = "hw3"; break;
6871  case MipsInterruptAttr::hw4: Kind = "hw4"; break;
6872  case MipsInterruptAttr::hw5: Kind = "hw5"; break;
6873  }
6874 
6875  Fn->addFnAttr("interrupt", Kind);
6876 
6877  }
6878 
6879  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
6880  llvm::Value *Address) const override;
6881 
6882  unsigned getSizeOfUnwindException() const override {
6883  return SizeOfUnwindException;
6884  }
6885 };
6886 }
6887 
6888 void MipsABIInfo::CoerceToIntArgs(
6889  uint64_t TySize, SmallVectorImpl<llvm::Type *> &ArgList) const {
6890  llvm::IntegerType *IntTy =
6891  llvm::IntegerType::get(getVMContext(), MinABIStackAlignInBytes * 8);
6892 
6893  // Add (TySize / MinABIStackAlignInBytes) args of IntTy.
6894  for (unsigned N = TySize / (MinABIStackAlignInBytes * 8); N; --N)
6895  ArgList.push_back(IntTy);
6896 
6897  // If necessary, add one more integer type to ArgList.
6898  unsigned R = TySize % (MinABIStackAlignInBytes * 8);
6899 
6900  if (R)
6901  ArgList.push_back(llvm::IntegerType::get(getVMContext(), R));
6902 }
6903 
6904 // In N32/64, an aligned double precision floating point field is passed in
6905 // a register.
6906 llvm::Type* MipsABIInfo::HandleAggregates(QualType Ty, uint64_t TySize) const {
6907  SmallVector<llvm::Type*, 8> ArgList, IntArgList;
6908 
6909  if (IsO32) {
6910  CoerceToIntArgs(TySize, ArgList);
6911  return llvm::StructType::get(getVMContext(), ArgList);
6912  }
6913 
6914  if (Ty->isComplexType())
6915  return CGT.ConvertType(Ty);
6916 
6917  const RecordType *RT = Ty->getAs<RecordType>();
6918 
6919  // Unions/vectors are passed in integer registers.
6920  if (!RT || !RT->isStructureOrClassType()) {
6921  CoerceToIntArgs(TySize, ArgList);
6922  return llvm::StructType::get(getVMContext(), ArgList);
6923  }
6924 
6925  const RecordDecl *RD = RT->getDecl();
6926  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
6927  assert(!(TySize % 8) && "Size of structure must be multiple of 8.");
6928 
6929  uint64_t LastOffset = 0;
6930  unsigned idx = 0;
6931  llvm::IntegerType *I64 = llvm::IntegerType::get(getVMContext(), 64);
6932 
6933  // Iterate over fields in the struct/class and check if there are any aligned
6934  // double fields.
6935  for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
6936  i != e; ++i, ++idx) {
6937  const QualType Ty = i->getType();
6938  const BuiltinType *BT = Ty->getAs<BuiltinType>();
6939 
6940  if (!BT || BT->getKind() != BuiltinType::Double)
6941  continue;
6942 
6943  uint64_t Offset = Layout.getFieldOffset(idx);
6944  if (Offset % 64) // Ignore doubles that are not aligned.
6945  continue;
6946 
6947  // Add ((Offset - LastOffset) / 64) args of type i64.
6948  for (unsigned j = (Offset - LastOffset) / 64; j > 0; --j)
6949  ArgList.push_back(I64);
6950 
6951  // Add double type.
6952  ArgList.push_back(llvm::Type::getDoubleTy(getVMContext()));
6953  LastOffset = Offset + 64;
6954  }
6955 
6956  CoerceToIntArgs(TySize - LastOffset, IntArgList);
6957  ArgList.append(IntArgList.begin(), IntArgList.end());
6958 
6959  return llvm::StructType::get(getVMContext(), ArgList);
6960 }
6961 
6962 llvm::Type *MipsABIInfo::getPaddingType(uint64_t OrigOffset,
6963  uint64_t Offset) const {
6964  if (OrigOffset + MinABIStackAlignInBytes > Offset)
6965  return nullptr;
6966 
6967  return llvm::IntegerType::get(getVMContext(), (Offset - OrigOffset) * 8);
6968 }
6969 
6970 ABIArgInfo
6971 MipsABIInfo::classifyArgumentType(QualType Ty, uint64_t &Offset) const {
6973 
6974  uint64_t OrigOffset = Offset;
6975  uint64_t TySize = getContext().getTypeSize(Ty);
6976  uint64_t Align = getContext().getTypeAlign(Ty) / 8;
6977 
6978  Align = std::min(std::max(Align, (uint64_t)MinABIStackAlignInBytes),
6979  (uint64_t)StackAlignInBytes);
6980  unsigned CurrOffset = llvm::alignTo(Offset, Align);
6981  Offset = CurrOffset + llvm::alignTo(TySize, Align * 8) / 8;
6982 
6983  if (isAggregateTypeForABI(Ty) || Ty->isVectorType()) {
6984  // Ignore empty aggregates.
6985  if (TySize == 0)
6986  return ABIArgInfo::getIgnore();
6987 
6989  Offset = OrigOffset + MinABIStackAlignInBytes;
6991  }
6992 
6993  // If we have reached here, aggregates are passed directly by coercing to
6994  // another structure type. Padding is inserted if the offset of the
6995  // aggregate is unaligned.
6996  ABIArgInfo ArgInfo =
6997  ABIArgInfo::getDirect(HandleAggregates(Ty, TySize), 0,
6998  getPaddingType(OrigOffset, CurrOffset));
6999  ArgInfo.setInReg(true);
7000  return ArgInfo;
7001  }
7002 
7003  // Treat an enum type as its underlying type.
7004  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7005  Ty = EnumTy->getDecl()->getIntegerType();
7006 
7007  // All integral types are promoted to the GPR width.
7008  if (Ty->isIntegralOrEnumerationType())
7009  return extendType(Ty);
7010 
7011  return ABIArgInfo::getDirect(
7012  nullptr, 0, IsO32 ? nullptr : getPaddingType(OrigOffset, CurrOffset));
7013 }
7014 
7015 llvm::Type*
7016 MipsABIInfo::returnAggregateInRegs(QualType RetTy, uint64_t Size) const {
7017  const RecordType *RT = RetTy->getAs<RecordType>();
7019 
7020  if (RT && RT->isStructureOrClassType()) {
7021  const RecordDecl *RD = RT->getDecl();
7022  const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
7023  unsigned FieldCnt = Layout.getFieldCount();
7024 
7025  // N32/64 returns struct/classes in floating point registers if the
7026  // following conditions are met:
7027  // 1. The size of the struct/class is no larger than 128-bit.
7028  // 2. The struct/class has one or two fields all of which are floating
7029  // point types.
7030  // 3. The offset of the first field is zero (this follows what gcc does).
7031  //
7032  // Any other composite results are returned in integer registers.
7033  //
7034  if (FieldCnt && (FieldCnt <= 2) && !Layout.getFieldOffset(0)) {
7035  RecordDecl::field_iterator b = RD->field_begin(), e = RD->field_end();
7036  for (; b != e; ++b) {
7037  const BuiltinType *BT = b->getType()->getAs<BuiltinType>();
7038 
7039  if (!BT || !BT->isFloatingPoint())
7040  break;
7041 
7042  RTList.push_back(CGT.ConvertType(b->getType()));
7043  }
7044 
7045  if (b == e)
7046  return llvm::StructType::get(getVMContext(), RTList,
7047  RD->hasAttr<PackedAttr>());
7048 
7049  RTList.clear();
7050  }
7051  }
7052 
7053  CoerceToIntArgs(Size, RTList);
7054  return llvm::StructType::get(getVMContext(), RTList);
7055 }
7056 
7058  uint64_t Size = getContext().getTypeSize(RetTy);
7059 
7060  if (RetTy->isVoidType())
7061  return ABIArgInfo::getIgnore();
7062 
7063  // O32 doesn't treat zero-sized structs differently from other structs.
7064  // However, N32/N64 ignores zero sized return values.
7065  if (!IsO32 && Size == 0)
7066  return ABIArgInfo::getIgnore();
7067 
7068  if (isAggregateTypeForABI(RetTy) || RetTy->isVectorType()) {
7069  if (Size <= 128) {
7070  if (RetTy->isAnyComplexType())
7071  return ABIArgInfo::getDirect();
7072 
7073  // O32 returns integer vectors in registers and N32/N64 returns all small
7074  // aggregates in registers.
7075  if (!IsO32 ||
7076  (RetTy->isVectorType() && !RetTy->hasFloatingRepresentation())) {
7077  ABIArgInfo ArgInfo =
7078  ABIArgInfo::getDirect(returnAggregateInRegs(RetTy, Size));
7079  ArgInfo.setInReg(true);
7080  return ArgInfo;
7081  }
7082  }
7083 
7084  return getNaturalAlignIndirect(RetTy);
7085  }
7086 
7087  // Treat an enum type as its underlying type.
7088  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7089  RetTy = EnumTy->getDecl()->getIntegerType();
7090 
7091  if (RetTy->isPromotableIntegerType())
7092  return ABIArgInfo::getExtend(RetTy);
7093 
7094  if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
7095  RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
7096  return ABIArgInfo::getSignExtend(RetTy);
7097 
7098  return ABIArgInfo::getDirect();
7099 }
7100 
7101 void MipsABIInfo::computeInfo(CGFunctionInfo &FI) const {
7102  ABIArgInfo &RetInfo = FI.getReturnInfo();
7103  if (!getCXXABI().classifyReturnType(FI))
7104  RetInfo = classifyReturnType(FI.getReturnType());
7105 
7106  // Check if a pointer to an aggregate is passed as a hidden argument.
7107  uint64_t Offset = RetInfo.isIndirect() ? MinABIStackAlignInBytes : 0;
7108 
7109  for (auto &I : FI.arguments())
7110  I.info = classifyArgumentType(I.type, Offset);
7111 }
7112 
7113 Address MipsABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7114  QualType OrigTy) const {
7115  QualType Ty = OrigTy;
7116 
7117  // Integer arguments are promoted to 32-bit on O32 and 64-bit on N32/N64.
7118  // Pointers are also promoted in the same way but this only matters for N32.
7119  unsigned SlotSizeInBits = IsO32 ? 32 : 64;
7120  unsigned PtrWidth = getTarget().getPointerWidth(0);
7121  bool DidPromote = false;
7122  if ((Ty->isIntegerType() &&
7123  getContext().getIntWidth(Ty) < SlotSizeInBits) ||
7124  (Ty->isPointerType() && PtrWidth < SlotSizeInBits)) {
7125  DidPromote = true;
7126  Ty = getContext().getIntTypeForBitwidth(SlotSizeInBits,
7127  Ty->isSignedIntegerType());
7128  }
7129 
7130  auto TyInfo = getContext().getTypeInfoInChars(Ty);
7131 
7132  // The alignment of things in the argument area is never larger than
7133  // StackAlignInBytes.
7134  TyInfo.second =
7135  std::min(TyInfo.second, CharUnits::fromQuantity(StackAlignInBytes));
7136 
7137  // MinABIStackAlignInBytes is the size of argument slots on the stack.
7138  CharUnits ArgSlotSize = CharUnits::fromQuantity(MinABIStackAlignInBytes);
7139 
7140  Address Addr = emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7141  TyInfo, ArgSlotSize, /*AllowHigherAlign*/ true);
7142 
7143 
7144  // If there was a promotion, "unpromote" into a temporary.
7145  // TODO: can we just use a pointer into a subset of the original slot?
7146  if (DidPromote) {
7147  Address Temp = CGF.CreateMemTemp(OrigTy, "vaarg.promotion-temp");
7148  llvm::Value *Promoted = CGF.Builder.CreateLoad(Addr);
7149 
7150  // Truncate down to the right width.
7151  llvm::Type *IntTy = (OrigTy->isIntegerType() ? Temp.getElementType()
7152  : CGF.IntPtrTy);
7153  llvm::Value *V = CGF.Builder.CreateTrunc(Promoted, IntTy);
7154  if (OrigTy->isPointerType())
7155  V = CGF.Builder.CreateIntToPtr(V, Temp.getElementType());
7156 
7157  CGF.Builder.CreateStore(V, Temp);
7158  Addr = Temp;
7159  }
7160 
7161  return Addr;
7162 }
7163 
7164 ABIArgInfo MipsABIInfo::extendType(QualType Ty) const {
7165  int TySize = getContext().getTypeSize(Ty);
7166 
7167  // MIPS64 ABI requires unsigned 32 bit integers to be sign extended.
7168  if (Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
7169  return ABIArgInfo::getSignExtend(Ty);
7170 
7171  return ABIArgInfo::getExtend(Ty);
7172 }
7173 
7174 bool
7175 MIPSTargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
7176  llvm::Value *Address) const {
7177  // This information comes from gcc's implementation, which seems to
7178  // as canonical as it gets.
7179 
7180  // Everything on MIPS is 4 bytes. Double-precision FP registers
7181  // are aliased to pairs of single-precision FP registers.
7182  llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4);
7183 
7184  // 0-31 are the general purpose registers, $0 - $31.
7185  // 32-63 are the floating-point registers, $f0 - $f31.
7186  // 64 and 65 are the multiply/divide registers, $hi and $lo.
7187  // 66 is the (notional, I think) register for signal-handler return.
7188  AssignToArrayRange(CGF.Builder, Address, Four8, 0, 65);
7189 
7190  // 67-74 are the floating-point status registers, $fcc0 - $fcc7.
7191  // They are one bit wide and ignored here.
7192 
7193  // 80-111 are the coprocessor 0 registers, $c0r0 - $c0r31.
7194  // (coprocessor 1 is the FP unit)
7195  // 112-143 are the coprocessor 2 registers, $c2r0 - $c2r31.
7196  // 144-175 are the coprocessor 3 registers, $c3r0 - $c3r31.
7197  // 176-181 are the DSP accumulator registers.
7198  AssignToArrayRange(CGF.Builder, Address, Four8, 80, 181);
7199  return false;
7200 }
7201 
7202 //===----------------------------------------------------------------------===//
7203 // AVR ABI Implementation.
7204 //===----------------------------------------------------------------------===//
7205 
7206 namespace {
7207 class AVRTargetCodeGenInfo : public TargetCodeGenInfo {
7208 public:
7209  AVRTargetCodeGenInfo(CodeGenTypes &CGT)
7210  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) { }
7211 
7212  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7213  CodeGen::CodeGenModule &CGM) const override {
7214  if (GV->isDeclaration())
7215  return;
7216  const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
7217  if (!FD) return;
7218  auto *Fn = cast<llvm::Function>(GV);
7219 
7220  if (FD->getAttr<AVRInterruptAttr>())
7221  Fn->addFnAttr("interrupt");
7222 
7223  if (FD->getAttr<AVRSignalAttr>())
7224  Fn->addFnAttr("signal");
7225  }
7226 };
7227 }
7228 
7229 //===----------------------------------------------------------------------===//
7230 // TCE ABI Implementation (see http://tce.cs.tut.fi). Uses mostly the defaults.
7231 // Currently subclassed only to implement custom OpenCL C function attribute
7232 // handling.
7233 //===----------------------------------------------------------------------===//
7234 
7235 namespace {
7236 
7237 class TCETargetCodeGenInfo : public DefaultTargetCodeGenInfo {
7238 public:
7239  TCETargetCodeGenInfo(CodeGenTypes &CGT)
7240  : DefaultTargetCodeGenInfo(CGT) {}
7241 
7242  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7243  CodeGen::CodeGenModule &M) const override;
7244 };
7245 
7246 void TCETargetCodeGenInfo::setTargetAttributes(
7247  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7248  if (GV->isDeclaration())
7249  return;
7250  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7251  if (!FD) return;
7252 
7253  llvm::Function *F = cast<llvm::Function>(GV);
7254 
7255  if (M.getLangOpts().OpenCL) {
7256  if (FD->hasAttr<OpenCLKernelAttr>()) {
7257  // OpenCL C Kernel functions are not subject to inlining
7258  F->addFnAttr(llvm::Attribute::NoInline);
7259  const ReqdWorkGroupSizeAttr *Attr = FD->getAttr<ReqdWorkGroupSizeAttr>();
7260  if (Attr) {
7261  // Convert the reqd_work_group_size() attributes to metadata.
7262  llvm::LLVMContext &Context = F->getContext();
7263  llvm::NamedMDNode *OpenCLMetadata =
7264  M.getModule().getOrInsertNamedMetadata(
7265  "opencl.kernel_wg_size_info");
7266 
7268  Operands.push_back(llvm::ConstantAsMetadata::get(F));
7269 
7270  Operands.push_back(
7271  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7272  M.Int32Ty, llvm::APInt(32, Attr->getXDim()))));
7273  Operands.push_back(
7274  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7275  M.Int32Ty, llvm::APInt(32, Attr->getYDim()))));
7276  Operands.push_back(
7277  llvm::ConstantAsMetadata::get(llvm::Constant::getIntegerValue(
7278  M.Int32Ty, llvm::APInt(32, Attr->getZDim()))));
7279 
7280  // Add a boolean constant operand for "required" (true) or "hint"
7281  // (false) for implementing the work_group_size_hint attr later.
7282  // Currently always true as the hint is not yet implemented.
7283  Operands.push_back(
7284  llvm::ConstantAsMetadata::get(llvm::ConstantInt::getTrue(Context)));
7285  OpenCLMetadata->addOperand(llvm::MDNode::get(Context, Operands));
7286  }
7287  }
7288  }
7289 }
7290 
7291 }
7292 
7293 //===----------------------------------------------------------------------===//
7294 // Hexagon ABI Implementation
7295 //===----------------------------------------------------------------------===//
7296 
7297 namespace {
7298 
7299 class HexagonABIInfo : public ABIInfo {
7300 
7301 
7302 public:
7303  HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7304 
7305 private:
7306 
7307  ABIArgInfo classifyReturnType(QualType RetTy) const;
7309 
7310  void computeInfo(CGFunctionInfo &FI) const override;
7311 
7312  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7313  QualType Ty) const override;
7314 };
7315 
7316 class HexagonTargetCodeGenInfo : public TargetCodeGenInfo {
7317 public:
7318  HexagonTargetCodeGenInfo(CodeGenTypes &CGT)
7319  :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {}
7320 
7321  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
7322  return 29;
7323  }
7324 };
7325 
7326 }
7327 
7328 void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const {
7329  if (!getCXXABI().classifyReturnType(FI))
7331  for (auto &I : FI.arguments())
7332  I.info = classifyArgumentType(I.type);
7333 }
7334 
7336  if (!isAggregateTypeForABI(Ty)) {
7337  // Treat an enum type as its underlying type.
7338  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
7339  Ty = EnumTy->getDecl()->getIntegerType();
7340 
7342  : ABIArgInfo::getDirect());
7343  }
7344 
7347 
7348  // Ignore empty records.
7349  if (isEmptyRecord(getContext(), Ty, true))
7350  return ABIArgInfo::getIgnore();
7351 
7352  uint64_t Size = getContext().getTypeSize(Ty);
7353  if (Size > 64)
7354  return getNaturalAlignIndirect(Ty, /*ByVal=*/true);
7355  // Pass in the smallest viable integer type.
7356  else if (Size > 32)
7357  return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7358  else if (Size > 16)
7359  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7360  else if (Size > 8)
7361  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7362  else
7363  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7364 }
7365 
7367  if (RetTy->isVoidType())
7368  return ABIArgInfo::getIgnore();
7369 
7370  // Large vector types should be returned via memory.
7371  if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64)
7372  return getNaturalAlignIndirect(RetTy);
7373 
7374  if (!isAggregateTypeForABI(RetTy)) {
7375  // Treat an enum type as its underlying type.
7376  if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
7377  RetTy = EnumTy->getDecl()->getIntegerType();
7378 
7379  return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
7380  : ABIArgInfo::getDirect());
7381  }
7382 
7383  if (isEmptyRecord(getContext(), RetTy, true))
7384  return ABIArgInfo::getIgnore();
7385 
7386  // Aggregates <= 8 bytes are returned in r0; other aggregates
7387  // are returned indirectly.
7388  uint64_t Size = getContext().getTypeSize(RetTy);
7389  if (Size <= 64) {
7390  // Return in the smallest viable integer type.
7391  if (Size <= 8)
7392  return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext()));
7393  if (Size <= 16)
7394  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7395  if (Size <= 32)
7396  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7397  return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext()));
7398  }
7399 
7400  return getNaturalAlignIndirect(RetTy, /*ByVal=*/true);
7401 }
7402 
7403 Address HexagonABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7404  QualType Ty) const {
7405  // FIXME: Someone needs to audit that this handle alignment correctly.
7406  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
7407  getContext().getTypeInfoInChars(Ty),
7409  /*AllowHigherAlign*/ true);
7410 }
7411 
7412 //===----------------------------------------------------------------------===//
7413 // Lanai ABI Implementation
7414 //===----------------------------------------------------------------------===//
7415 
7416 namespace {
7417 class LanaiABIInfo : public DefaultABIInfo {
7418 public:
7419  LanaiABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7420 
7421  bool shouldUseInReg(QualType Ty, CCState &State) const;
7422 
7423  void computeInfo(CGFunctionInfo &FI) const override {
7424  CCState State(FI.getCallingConvention());
7425  // Lanai uses 4 registers to pass arguments unless the function has the
7426  // regparm attribute set.
7427  if (FI.getHasRegParm()) {
7428  State.FreeRegs = FI.getRegParm();
7429  } else {
7430  State.FreeRegs = 4;
7431  }
7432 
7433  if (!getCXXABI().classifyReturnType(FI))
7435  for (auto &I : FI.arguments())
7436  I.info = classifyArgumentType(I.type, State);
7437  }
7438 
7439  ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const;
7440  ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
7441 };
7442 } // end anonymous namespace
7443 
7444 bool LanaiABIInfo::shouldUseInReg(QualType Ty, CCState &State) const {
7445  unsigned Size = getContext().getTypeSize(Ty);
7446  unsigned SizeInRegs = llvm::alignTo(Size, 32U) / 32U;
7447 
7448  if (SizeInRegs == 0)
7449  return false;
7450 
7451  if (SizeInRegs > State.FreeRegs) {
7452  State.FreeRegs = 0;
7453  return false;
7454  }
7455 
7456  State.FreeRegs -= SizeInRegs;
7457 
7458  return true;
7459 }
7460 
7461 ABIArgInfo LanaiABIInfo::getIndirectResult(QualType Ty, bool ByVal,
7462  CCState &State) const {
7463  if (!ByVal) {
7464  if (State.FreeRegs) {
7465  --State.FreeRegs; // Non-byval indirects just use one pointer.
7466  return getNaturalAlignIndirectInReg(Ty);
7467  }
7468  return getNaturalAlignIndirect(Ty, false);
7469  }
7470 
7471  // Compute the byval alignment.
7472  const unsigned MinABIStackAlignInBytes = 4;
7473  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
7474  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
7475  /*Realign=*/TypeAlign >
7476  MinABIStackAlignInBytes);
7477 }
7478 
7480  CCState &State) const {
7481  // Check with the C++ ABI first.
7482  const RecordType *RT = Ty->getAs<RecordType>();
7483  if (RT) {
7485  if (RAA == CGCXXABI::RAA_Indirect) {
7486  return getIndirectResult(Ty, /*ByVal=*/false, State);
7487  } else if (RAA == CGCXXABI::RAA_DirectInMemory) {
7488  return getNaturalAlignIndirect(Ty, /*ByRef=*/true);
7489  }
7490  }
7491 
7492  if (isAggregateTypeForABI(Ty)) {
7493  // Structures with flexible arrays are always indirect.
7494  if (RT && RT->getDecl()->hasFlexibleArrayMember())
7495  return getIndirectResult(Ty, /*ByVal=*/true, State);
7496 
7497  // Ignore empty structs/unions.
7498  if (isEmptyRecord(getContext(), Ty, true))
7499  return ABIArgInfo::getIgnore();
7500 
7501  llvm::LLVMContext &LLVMContext = getVMContext();
7502  unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32;
7503  if (SizeInRegs <= State.FreeRegs) {
7504  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
7505  SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
7506  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
7507  State.FreeRegs -= SizeInRegs;
7508  return ABIArgInfo::getDirectInReg(Result);
7509  } else {
7510  State.FreeRegs = 0;
7511  }
7512  return getIndirectResult(Ty, true, State);
7513  }
7514 
7515  // Treat an enum type as its underlying type.
7516  if (const auto *EnumTy = Ty->getAs<EnumType>())
7517  Ty = EnumTy->getDecl()->getIntegerType();
7518 
7519  bool InReg = shouldUseInReg(Ty, State);
7520  if (Ty->isPromotableIntegerType()) {
7521  if (InReg)
7522  return ABIArgInfo::getDirectInReg();
7523  return ABIArgInfo::getExtend(Ty);
7524  }
7525  if (InReg)
7526  return ABIArgInfo::getDirectInReg();
7527  return ABIArgInfo::getDirect();
7528 }
7529 
7530 namespace {
7531 class LanaiTargetCodeGenInfo : public TargetCodeGenInfo {
7532 public:
7533  LanaiTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
7534  : TargetCodeGenInfo(new LanaiABIInfo(CGT)) {}
7535 };
7536 }
7537 
7538 //===----------------------------------------------------------------------===//
7539 // AMDGPU ABI Implementation
7540 //===----------------------------------------------------------------------===//
7541 
7542 namespace {
7543 
7544 class AMDGPUABIInfo final : public DefaultABIInfo {
7545 private:
7546  static const unsigned MaxNumRegsForArgsRet = 16;
7547 
7548  unsigned numRegsForType(QualType Ty) const;
7549 
7550  bool isHomogeneousAggregateBaseType(QualType Ty) const override;
7551  bool isHomogeneousAggregateSmallEnough(const Type *Base,
7552  uint64_t Members) const override;
7553 
7554 public:
7555  explicit AMDGPUABIInfo(CodeGen::CodeGenTypes &CGT) :
7556  DefaultABIInfo(CGT) {}
7557 
7558  ABIArgInfo classifyReturnType(QualType RetTy) const;
7559  ABIArgInfo classifyKernelArgumentType(QualType Ty) const;
7560  ABIArgInfo classifyArgumentType(QualType Ty, unsigned &NumRegsLeft) const;
7561 
7562  void computeInfo(CGFunctionInfo &FI) const override;
7563 };
7564 
7565 bool AMDGPUABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
7566  return true;
7567 }
7568 
7569 bool AMDGPUABIInfo::isHomogeneousAggregateSmallEnough(
7570  const Type *Base, uint64_t Members) const {
7571  uint32_t NumRegs = (getContext().getTypeSize(Base) + 31) / 32;
7572 
7573  // Homogeneous Aggregates may occupy at most 16 registers.
7574  return Members * NumRegs <= MaxNumRegsForArgsRet;
7575 }
7576 
7577 /// Estimate number of registers the type will use when passed in registers.
7578 unsigned AMDGPUABIInfo::numRegsForType(QualType Ty) const {
7579  unsigned NumRegs = 0;
7580 
7581  if (const VectorType *VT = Ty->getAs<VectorType>()) {
7582  // Compute from the number of elements. The reported size is based on the
7583  // in-memory size, which includes the padding 4th element for 3-vectors.
7584  QualType EltTy = VT->getElementType();
7585  unsigned EltSize = getContext().getTypeSize(EltTy);
7586 
7587  // 16-bit element vectors should be passed as packed.
7588  if (EltSize == 16)
7589  return (VT->getNumElements() + 1) / 2;
7590 
7591  unsigned EltNumRegs = (EltSize + 31) / 32;
7592  return EltNumRegs * VT->getNumElements();
7593  }
7594 
7595  if (const RecordType *RT = Ty->getAs<RecordType>()) {
7596  const RecordDecl *RD = RT->getDecl();
7597  assert(!RD->hasFlexibleArrayMember());
7598 
7599  for (const FieldDecl *Field : RD->fields()) {
7600  QualType FieldTy = Field->getType();
7601  NumRegs += numRegsForType(FieldTy);
7602  }
7603 
7604  return NumRegs;
7605  }
7606 
7607  return (getContext().getTypeSize(Ty) + 31) / 32;
7608 }
7609 
7610 void AMDGPUABIInfo::computeInfo(CGFunctionInfo &FI) const {
7612 
7613  if (!getCXXABI().classifyReturnType(FI))
7615 
7616  unsigned NumRegsLeft = MaxNumRegsForArgsRet;
7617  for (auto &Arg : FI.arguments()) {
7618  if (CC == llvm::CallingConv::AMDGPU_KERNEL) {
7619  Arg.info = classifyKernelArgumentType(Arg.type);
7620  } else {
7621  Arg.info = classifyArgumentType(Arg.type, NumRegsLeft);
7622  }
7623  }
7624 }
7625 
7627  if (isAggregateTypeForABI(RetTy)) {
7628  // Records with non-trivial destructors/copy-constructors should not be
7629  // returned by value.
7630  if (!getRecordArgABI(RetTy, getCXXABI())) {
7631  // Ignore empty structs/unions.
7632  if (isEmptyRecord(getContext(), RetTy, true))
7633  return ABIArgInfo::getIgnore();
7634 
7635  // Lower single-element structs to just return a regular value.
7636  if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext()))
7637  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7638 
7639  if (const RecordType *RT = RetTy->getAs<RecordType>()) {
7640  const RecordDecl *RD = RT->getDecl();
7641  if (RD->hasFlexibleArrayMember())
7642  return DefaultABIInfo::classifyReturnType(RetTy);
7643  }
7644 
7645  // Pack aggregates <= 4 bytes into single VGPR or pair.
7646  uint64_t Size = getContext().getTypeSize(RetTy);
7647  if (Size <= 16)
7648  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7649 
7650  if (Size <= 32)
7651  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7652 
7653  if (Size <= 64) {
7654  llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7655  return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7656  }
7657 
7658  if (numRegsForType(RetTy) <= MaxNumRegsForArgsRet)
7659  return ABIArgInfo::getDirect();
7660  }
7661  }
7662 
7663  // Otherwise just do the default thing.
7664  return DefaultABIInfo::classifyReturnType(RetTy);
7665 }
7666 
7667 /// For kernels all parameters are really passed in a special buffer. It doesn't
7668 /// make sense to pass anything byval, so everything must be direct.
7669 ABIArgInfo AMDGPUABIInfo::classifyKernelArgumentType(QualType Ty) const {
7671 
7672  // TODO: Can we omit empty structs?
7673 
7674  // Coerce single element structs to its element.
7675  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7676  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7677 
7678  // If we set CanBeFlattened to true, CodeGen will expand the struct to its
7679  // individual elements, which confuses the Clover OpenCL backend; therefore we
7680  // have to set it to false here. Other args of getDirect() are just defaults.
7681  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
7682 }
7683 
7685  unsigned &NumRegsLeft) const {
7686  assert(NumRegsLeft <= MaxNumRegsForArgsRet && "register estimate underflow");
7687 
7689 
7690  if (isAggregateTypeForABI(Ty)) {
7691  // Records with non-trivial destructors/copy-constructors should not be
7692  // passed by value.
7693  if (auto RAA = getRecordArgABI(Ty, getCXXABI()))
7695 
7696  // Ignore empty structs/unions.
7697  if (isEmptyRecord(getContext(), Ty, true))
7698  return ABIArgInfo::getIgnore();
7699 
7700  // Lower single-element structs to just pass a regular value. TODO: We
7701  // could do reasonable-size multiple-element structs too, using getExpand(),
7702  // though watch out for things like bitfields.
7703  if (const Type *SeltTy = isSingleElementStruct(Ty, getContext()))
7704  return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0)));
7705 
7706  if (const RecordType *RT = Ty->getAs<RecordType>()) {
7707  const RecordDecl *RD = RT->getDecl();
7708  if (RD->hasFlexibleArrayMember())
7710  }
7711 
7712  // Pack aggregates <= 8 bytes into single VGPR or pair.
7713  uint64_t Size = getContext().getTypeSize(Ty);
7714  if (Size <= 64) {
7715  unsigned NumRegs = (Size + 31) / 32;
7716  NumRegsLeft -= std::min(NumRegsLeft, NumRegs);
7717 
7718  if (Size <= 16)
7719  return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext()));
7720 
7721  if (Size <= 32)
7722  return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext()));
7723 
7724  // XXX: Should this be i64 instead, and should the limit increase?
7725  llvm::Type *I32Ty = llvm::Type::getInt32Ty(getVMContext());
7726  return ABIArgInfo::getDirect(llvm::ArrayType::get(I32Ty, 2));
7727  }
7728 
7729  if (NumRegsLeft > 0) {
7730  unsigned NumRegs = numRegsForType(Ty);
7731  if (NumRegsLeft >= NumRegs) {
7732  NumRegsLeft -= NumRegs;
7733  return ABIArgInfo::getDirect();
7734  }
7735  }
7736  }
7737 
7738  // Otherwise just do the default thing.
7740  if (!ArgInfo.isIndirect()) {
7741  unsigned NumRegs = numRegsForType(Ty);
7742  NumRegsLeft -= std::min(NumRegs, NumRegsLeft);
7743  }
7744 
7745  return ArgInfo;
7746 }
7747 
7748 class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
7749 public:
7750  AMDGPUTargetCodeGenInfo(CodeGenTypes &CGT)
7751  : TargetCodeGenInfo(new AMDGPUABIInfo(CGT)) {}
7752  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
7753  CodeGen::CodeGenModule &M) const override;
7754  unsigned getOpenCLKernelCallingConv() const override;
7755 
7756  llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
7757  llvm::PointerType *T, QualType QT) const override;
7758 
7759  LangAS getASTAllocaAddressSpace() const override {
7760  return getLangASFromTargetAS(
7761  getABIInfo().getDataLayout().getAllocaAddrSpace());
7762  }
7763  LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
7764  const VarDecl *D) const override;
7765  llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S,
7766  llvm::LLVMContext &C) const override;
7767  llvm::Function *
7768  createEnqueuedBlockKernel(CodeGenFunction &CGF,
7769  llvm::Function *BlockInvokeFunc,
7770  llvm::Value *BlockLiteral) const override;
7771  bool shouldEmitStaticExternCAliases() const override;
7772  void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
7773 };
7774 }
7775 
7776 void AMDGPUTargetCodeGenInfo::setTargetAttributes(
7777  const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
7778  if (GV->isDeclaration())
7779  return;
7780  const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
7781  if (!FD)
7782  return;
7783 
7784  llvm::Function *F = cast<llvm::Function>(GV);
7785 
7786  const auto *ReqdWGS = M.getLangOpts().OpenCL ?
7787  FD->getAttr<ReqdWorkGroupSizeAttr>() : nullptr;
7788 
7789  if (M.getLangOpts().OpenCL && FD->hasAttr<OpenCLKernelAttr>() &&
7790  (M.getTriple().getOS() == llvm::Triple::AMDHSA))
7791  F->addFnAttr("amdgpu-implicitarg-num-bytes", "48");
7792 
7793  const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
7794  if (ReqdWGS || FlatWGS) {
7795  unsigned Min = FlatWGS ? FlatWGS->getMin() : 0;
7796  unsigned Max = FlatWGS ? FlatWGS->getMax() : 0;
7797  if (ReqdWGS && Min == 0 && Max == 0)
7798  Min = Max = ReqdWGS->getXDim() * ReqdWGS->getYDim() * ReqdWGS->getZDim();
7799 
7800  if (Min != 0) {
7801  assert(Min <= Max && "Min must be less than or equal Max");
7802 
7803  std::string AttrVal = llvm::utostr(Min) + "," + llvm::utostr(Max);
7804  F->addFnAttr("amdgpu-flat-work-group-size", AttrVal);
7805  } else
7806  assert(Max == 0 && "Max must be zero");
7807  }
7808 
7809  if (const auto *Attr = FD->getAttr<AMDGPUWavesPerEUAttr>()) {
7810  unsigned Min = Attr->getMin();
7811  unsigned Max = Attr->getMax();
7812 
7813  if (Min != 0) {
7814  assert((Max == 0 || Min <= Max) && "Min must be less than or equal Max");
7815 
7816  std::string AttrVal = llvm::utostr(Min);
7817  if (Max != 0)
7818  AttrVal = AttrVal + "," + llvm::utostr(Max);
7819  F->addFnAttr("amdgpu-waves-per-eu", AttrVal);
7820  } else
7821  assert(Max == 0 && "Max must be zero");
7822  }
7823 
7824  if (const auto *Attr = FD->getAttr<AMDGPUNumSGPRAttr>()) {
7825  unsigned NumSGPR = Attr->getNumSGPR();
7826 
7827  if (NumSGPR != 0)
7828  F->addFnAttr("amdgpu-num-sgpr", llvm::utostr(NumSGPR));
7829  }
7830 
7831  if (const auto *Attr = FD->getAttr<AMDGPUNumVGPRAttr>()) {
7832  uint32_t NumVGPR = Attr->getNumVGPR();
7833 
7834  if (NumVGPR != 0)
7835  F->addFnAttr("amdgpu-num-vgpr", llvm::utostr(NumVGPR));
7836  }
7837 }
7838 
7839 unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
7840  return llvm::CallingConv::AMDGPU_KERNEL;
7841 }
7842 
7843 // Currently LLVM assumes null pointers always have value 0,
7844 // which results in incorrectly transformed IR. Therefore, instead of
7845 // emitting null pointers in private and local address spaces, a null
7846 // pointer in generic address space is emitted which is casted to a
7847 // pointer in local or private address space.
7848 llvm::Constant *AMDGPUTargetCodeGenInfo::getNullPointer(
7849  const CodeGen::CodeGenModule &CGM, llvm::PointerType *PT,
7850  QualType QT) const {
7851  if (CGM.getContext().getTargetNullPointerValue(QT) == 0)
7852  return llvm::ConstantPointerNull::get(PT);
7853 
7854  auto &Ctx = CGM.getContext();
7855  auto NPT = llvm::PointerType::get(PT->getElementType(),
7856  Ctx.getTargetAddressSpace(LangAS::opencl_generic));
7857  return llvm::ConstantExpr::getAddrSpaceCast(
7858  llvm::ConstantPointerNull::get(NPT), PT);
7859 }
7860 
7861 LangAS
7862 AMDGPUTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
7863  const VarDecl *D) const {
7864  assert(!CGM.getLangOpts().OpenCL &&
7865  !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
7866  "Address space agnostic languages only");
7867  LangAS DefaultGlobalAS = getLangASFromTargetAS(
7869  if (!D)
7870  return DefaultGlobalAS;
7871 
7872  LangAS AddrSpace = D->getType().getAddressSpace();
7873  assert(AddrSpace == LangAS::Default || isTargetAddressSpace(AddrSpace));
7874  if (AddrSpace != LangAS::Default)
7875  return AddrSpace;
7876 
7877  if (CGM.isTypeConstant(D->getType(), false)) {
7878  if (auto ConstAS = CGM.getTarget().getConstantAddressSpace())
7879  return ConstAS.getValue();
7880  }
7881  return DefaultGlobalAS;
7882 }
7883 
7885 AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S,
7886  llvm::LLVMContext &C) const {
7887  StringRef Name;
7888  switch (S) {
7890  Name = "workgroup";
7891  break;
7893  Name = "agent";
7894  break;
7896  Name = "";
7897  break;
7899  Name = "subgroup";
7900  }
7901  return C.getOrInsertSyncScopeID(Name);
7902 }
7903 
7904 bool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
7905  return false;
7906 }
7907 
7909  const FunctionType *&FT) const {
7910  FT = getABIInfo().getContext().adjustFunctionType(
7912 }
7913 
7914 //===----------------------------------------------------------------------===//
7915 // SPARC v8 ABI Implementation.
7916 // Based on the SPARC Compliance Definition version 2.4.1.
7917 //
7918 // Ensures that complex values are passed in registers.
7919 //
7920 namespace {
7921 class SparcV8ABIInfo : public DefaultABIInfo {
7922 public:
7923  SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
7924 
7925 private:
7926  ABIArgInfo classifyReturnType(QualType RetTy) const;
7927  void computeInfo(CGFunctionInfo &FI) const override;
7928 };
7929 } // end anonymous namespace
7930 
7931 
7932 ABIArgInfo
7934  if (Ty->isAnyComplexType()) {
7935  return ABIArgInfo::getDirect();
7936  }
7937  else {
7939  }
7940 }
7941 
7942 void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
7943 
7945  for (auto &Arg : FI.arguments())
7946  Arg.info = classifyArgumentType(Arg.type);
7947 }
7948 
7949 namespace {
7950 class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
7951 public:
7952  SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
7953  : TargetCodeGenInfo(new SparcV8ABIInfo(CGT)) {}
7954 };
7955 } // end anonymous namespace
7956 
7957 //===----------------------------------------------------------------------===//
7958 // SPARC v9 ABI Implementation.
7959 // Based on the SPARC Compliance Definition version 2.4.1.
7960 //
7961 // Function arguments a mapped to a nominal "parameter array" and promoted to
7962 // registers depending on their type. Each argument occupies 8 or 16 bytes in
7963 // the array, structs larger than 16 bytes are passed indirectly.
7964 //
7965 // One case requires special care:
7966 //
7967 // struct mixed {
7968 // int i;
7969 // float f;
7970 // };
7971 //
7972 // When a struct mixed is passed by value, it only occupies 8 bytes in the
7973 // parameter array, but the int is passed in an integer register, and the float
7974 // is passed in a floating point register. This is represented as two arguments
7975 // with the LLVM IR inreg attribute:
7976 //
7977 // declare void f(i32 inreg %i, float inreg %f)
7978 //
7979 // The code generator will only allocate 4 bytes from the parameter array for
7980 // the inreg arguments. All other arguments are allocated a multiple of 8
7981 // bytes.
7982 //
7983 namespace {
7984 class SparcV9ABIInfo : public ABIInfo {
7985 public:
7986  SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
7987 
7988 private:
7989  ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit) const;
7990  void computeInfo(CGFunctionInfo &FI) const override;
7991  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
7992  QualType Ty) const override;
7993 
7994  // Coercion type builder for structs passed in registers. The coercion type
7995  // serves two purposes:
7996  //
7997  // 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
7998  // in registers.
7999  // 2. Expose aligned floating point elements as first-level elements, so the
8000  // code generator knows to pass them in floating point registers.
8001  //
8002  // We also compute the InReg flag which indicates that the struct contains
8003  // aligned 32-bit floats.
8004  //
8005  struct CoerceBuilder {
8006  llvm::LLVMContext &Context;
8007  const llvm::DataLayout &DL;
8009  uint64_t Size;
8010  bool InReg;
8011 
8012  CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
8013  : Context(c), DL(dl), Size(0), InReg(false) {}
8014 
8015  // Pad Elems with integers until Size is ToSize.
8016  void pad(uint64_t ToSize) {
8017  assert(ToSize >= Size && "Cannot remove elements");
8018  if (ToSize == Size)
8019  return;
8020 
8021  // Finish the current 64-bit word.
8022  uint64_t Aligned = llvm::alignTo(Size, 64);
8023  if (Aligned > Size && Aligned <= ToSize) {
8024  Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
8025  Size = Aligned;
8026  }
8027 
8028  // Add whole 64-bit words.
8029  while (Size + 64 <= ToSize) {
8030  Elems.push_back(llvm::Type::getInt64Ty(Context));
8031  Size += 64;
8032  }
8033 
8034  // Final in-word padding.
8035  if (Size < ToSize) {
8036  Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
8037  Size = ToSize;
8038  }
8039  }
8040 
8041  // Add a floating point element at Offset.
8042  void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
8043  // Unaligned floats are treated as integers.
8044  if (Offset % Bits)
8045  return;
8046  // The InReg flag is only required if there are any floats < 64 bits.
8047  if (Bits < 64)
8048  InReg = true;
8049  pad(Offset);
8050  Elems.push_back(Ty);
8051  Size = Offset + Bits;
8052  }
8053 
8054  // Add a struct type to the coercion type, starting at Offset (in bits).
8055  void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
8056  const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
8057  for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
8058  llvm::Type *ElemTy = StrTy->getElementType(i);
8059  uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
8060  switch (ElemTy->getTypeID()) {
8061  case llvm::Type::StructTyID:
8062  addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
8063  break;
8064  case llvm::Type::FloatTyID:
8065  addFloat(ElemOffset, ElemTy, 32);
8066  break;
8067  case llvm::Type::DoubleTyID:
8068  addFloat(ElemOffset, ElemTy, 64);
8069  break;
8070  case llvm::Type::FP128TyID:
8071  addFloat(ElemOffset, ElemTy, 128);
8072  break;
8073  case llvm::Type::PointerTyID:
8074  if (ElemOffset % 64 == 0) {
8075  pad(ElemOffset);
8076  Elems.push_back(ElemTy);
8077  Size += 64;
8078  }
8079  break;
8080  default:
8081  break;
8082  }
8083  }
8084  }
8085 
8086  // Check if Ty is a usable substitute for the coercion type.
8087  bool isUsableType(llvm::StructType *Ty) const {
8088  return llvm::makeArrayRef(Elems) == Ty->elements();
8089  }
8090 
8091  // Get the coercion type as a literal struct type.
8092  llvm::Type *getType() const {
8093  if (Elems.size() == 1)
8094  return Elems.front();
8095  else
8096  return llvm::StructType::get(Context, Elems);
8097  }
8098  };
8099 };
8100 } // end anonymous namespace
8101 
8102 ABIArgInfo
8103 SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit) const {
8104  if (Ty->isVoidType())
8105  return ABIArgInfo::getIgnore();
8106 
8107  uint64_t Size = getContext().getTypeSize(Ty);
8108 
8109  // Anything too big to fit in registers is passed with an explicit indirect
8110  // pointer / sret pointer.
8111  if (Size > SizeLimit)
8112  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
8113 
8114  // Treat an enum type as its underlying type.
8115  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8116  Ty = EnumTy->getDecl()->getIntegerType();
8117 
8118  // Integer types smaller than a register are extended.
8119  if (Size < 64 && Ty->isIntegerType())
8120  return ABIArgInfo::getExtend(Ty);
8121 
8122  // Other non-aggregates go in registers.
8123  if (!isAggregateTypeForABI(Ty))
8124  return ABIArgInfo::getDirect();
8125 
8126  // If a C++ object has either a non-trivial copy constructor or a non-trivial
8127  // destructor, it is passed with an explicit indirect pointer / sret pointer.
8130 
8131  // This is a small aggregate type that should be passed in registers.
8132  // Build a coercion type from the LLVM struct type.
8133  llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
8134  if (!StrTy)
8135  return ABIArgInfo::getDirect();
8136 
8137  CoerceBuilder CB(getVMContext(), getDataLayout());
8138  CB.addStruct(0, StrTy);
8139  CB.pad(llvm::alignTo(CB.DL.getTypeSizeInBits(StrTy), 64));
8140 
8141  // Try to use the original type for coercion.
8142  llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
8143 
8144  if (CB.InReg)
8145  return ABIArgInfo::getDirectInReg(CoerceTy);
8146  else
8147  return ABIArgInfo::getDirect(CoerceTy);
8148 }
8149 
8150 Address SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8151  QualType Ty) const {
8152  ABIArgInfo AI = classifyType(Ty, 16 * 8);
8153  llvm::Type *ArgTy = CGT.ConvertType(Ty);
8154  if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8155  AI.setCoerceToType(ArgTy);
8156 
8157  CharUnits SlotSize = CharUnits::fromQuantity(8);
8158 
8159  CGBuilderTy &Builder = CGF.Builder;
8160  Address Addr(Builder.CreateLoad(VAListAddr, "ap.cur"), SlotSize);
8161  llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8162 
8163  auto TypeInfo = getContext().getTypeInfoInChars(Ty);
8164 
8165  Address ArgAddr = Address::invalid();
8166  CharUnits Stride;
8167  switch (AI.getKind()) {
8168  case ABIArgInfo::Expand:
8170  case ABIArgInfo::InAlloca:
8171  llvm_unreachable("Unsupported ABI kind for va_arg");
8172 
8173  case ABIArgInfo::Extend: {
8174  Stride = SlotSize;
8175  CharUnits Offset = SlotSize - TypeInfo.first;
8176  ArgAddr = Builder.CreateConstInBoundsByteGEP(Addr, Offset, "extend");
8177  break;
8178  }
8179 
8180  case ABIArgInfo::Direct: {
8181  auto AllocSize = getDataLayout().getTypeAllocSize(AI.getCoerceToType());
8182  Stride = CharUnits::fromQuantity(AllocSize).alignTo(SlotSize);
8183  ArgAddr = Addr;
8184  break;
8185  }
8186 
8187  case ABIArgInfo::Indirect:
8188  Stride = SlotSize;
8189  ArgAddr = Builder.CreateElementBitCast(Addr, ArgPtrTy, "indirect");
8190  ArgAddr = Address(Builder.CreateLoad(ArgAddr, "indirect.arg"),
8191  TypeInfo.second);
8192  break;
8193 
8194  case ABIArgInfo::Ignore:
8195  return Address(llvm::UndefValue::get(ArgPtrTy), TypeInfo.second);
8196  }
8197 
8198  // Update VAList.
8199  llvm::Value *NextPtr =
8200  Builder.CreateConstInBoundsByteGEP(Addr.getPointer(), Stride, "ap.next");
8201  Builder.CreateStore(NextPtr, VAListAddr);
8202 
8203  return Builder.CreateBitCast(ArgAddr, ArgPtrTy, "arg.addr");
8204 }
8205 
8206 void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
8207  FI.getReturnInfo() = classifyType(FI.getReturnType(), 32 * 8);
8208  for (auto &I : FI.arguments())
8209  I.info = classifyType(I.type, 16 * 8);
8210 }
8211 
8212 namespace {
8213 class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
8214 public:
8215  SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
8216  : TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
8217 
8218  int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
8219  return 14;
8220  }
8221 
8222  bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8223  llvm::Value *Address) const override;
8224 };
8225 } // end anonymous namespace
8226 
8227 bool
8228 SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
8229  llvm::Value *Address) const {
8230  // This is calculated from the LLVM and GCC tables and verified
8231  // against gcc output. AFAIK all ABIs use the same encoding.
8232 
8233  CodeGen::CGBuilderTy &Builder = CGF.Builder;
8234 
8235  llvm::IntegerType *i8 = CGF.Int8Ty;
8236  llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
8237  llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
8238 
8239  // 0-31: the 8-byte general-purpose registers
8240  AssignToArrayRange(Builder, Address, Eight8, 0, 31);
8241 
8242  // 32-63: f0-31, the 4-byte floating-point registers
8243  AssignToArrayRange(Builder, Address, Four8, 32, 63);
8244 
8245  // Y = 64
8246  // PSR = 65
8247  // WIM = 66
8248  // TBR = 67
8249  // PC = 68
8250  // NPC = 69
8251  // FSR = 70
8252  // CSR = 71
8253  AssignToArrayRange(Builder, Address, Eight8, 64, 71);
8254 
8255  // 72-87: d0-15, the 8-byte floating-point registers
8256  AssignToArrayRange(Builder, Address, Eight8, 72, 87);
8257 
8258  return false;
8259 }
8260 
8261 // ARC ABI implementation.
8262 namespace {
8263 
8264 class ARCABIInfo : public DefaultABIInfo {
8265 public:
8266  using DefaultABIInfo::DefaultABIInfo;
8267 
8268 private:
8269  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8270  QualType Ty) const override;
8271 
8272  void updateState(const ABIArgInfo &Info, QualType Ty, CCState &State) const {
8273  if (!State.FreeRegs)
8274  return;
8275  if (Info.isIndirect() && Info.getInReg())
8276  State.FreeRegs--;
8277  else if (Info.isDirect() && Info.getInReg()) {
8278  unsigned sz = (getContext().getTypeSize(Ty) + 31) / 32;
8279  if (sz < State.FreeRegs)
8280  State.FreeRegs -= sz;
8281  else
8282  State.FreeRegs = 0;
8283  }
8284  }
8285 
8286  void computeInfo(CGFunctionInfo &FI) const override {
8287  CCState State(FI.getCallingConvention());
8288  // ARC uses 8 registers to pass arguments.
8289  State.FreeRegs = 8;
8290 
8291  if (!getCXXABI().classifyReturnType(FI))
8293  updateState(FI.getReturnInfo(), FI.getReturnType(), State);
8294  for (auto &I : FI.arguments()) {
8295  I.info = classifyArgumentType(I.type, State.FreeRegs);
8296  updateState(I.info, I.type, State);
8297  }
8298  }
8299 
8300  ABIArgInfo getIndirectByRef(QualType Ty, bool HasFreeRegs) const;
8301  ABIArgInfo getIndirectByValue(QualType Ty) const;
8302  ABIArgInfo classifyArgumentType(QualType Ty, uint8_t FreeRegs) const;
8303  ABIArgInfo classifyReturnType(QualType RetTy) const;
8304 };
8305 
8306 class ARCTargetCodeGenInfo : public TargetCodeGenInfo {
8307 public:
8308  ARCTargetCodeGenInfo(CodeGenTypes &CGT)
8309  : TargetCodeGenInfo(new ARCABIInfo(CGT)) {}
8310 };
8311 
8312 
8313 ABIArgInfo ARCABIInfo::getIndirectByRef(QualType Ty, bool HasFreeRegs) const {
8314  return HasFreeRegs ? getNaturalAlignIndirectInReg(Ty) :
8315  getNaturalAlignIndirect(Ty, false);
8316 }
8317 
8318 ABIArgInfo ARCABIInfo::getIndirectByValue(QualType Ty) const {
8319  // Compute the byval alignment.
8320  const unsigned MinABIStackAlignInBytes = 4;
8321  unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8;
8322  return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true,
8323  TypeAlign > MinABIStackAlignInBytes);
8324 }
8325 
8326 Address ARCABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8327  QualType Ty) const {
8328  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*indirect*/ false,
8329  getContext().getTypeInfoInChars(Ty),
8330  CharUnits::fromQuantity(4), true);
8331 }
8332 
8334  uint8_t FreeRegs) const {
8335  // Handle the generic C++ ABI.
8336  const RecordType *RT = Ty->getAs<RecordType>();
8337  if (RT) {
8339  if (RAA == CGCXXABI::RAA_Indirect)
8340  return getIndirectByRef(Ty, FreeRegs > 0);
8341 
8342  if (RAA == CGCXXABI::RAA_DirectInMemory)
8343  return getIndirectByValue(Ty);
8344  }
8345 
8346  // Treat an enum type as its underlying type.
8347  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
8348  Ty = EnumTy->getDecl()->getIntegerType();
8349 
8350  auto SizeInRegs = llvm::alignTo(getContext().getTypeSize(Ty), 32) / 32;
8351 
8352  if (isAggregateTypeForABI(Ty)) {
8353  // Structures with flexible arrays are always indirect.
8354  if (RT && RT->getDecl()->hasFlexibleArrayMember())
8355  return getIndirectByValue(Ty);
8356 
8357  // Ignore empty structs/unions.
8358  if (isEmptyRecord(getContext(), Ty, true))
8359  return ABIArgInfo::getIgnore();
8360 
8361  llvm::LLVMContext &LLVMContext = getVMContext();
8362 
8363  llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
8364  SmallVector<llvm::Type *, 3> Elements(SizeInRegs, Int32);
8365  llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements);
8366 
8367  return FreeRegs >= SizeInRegs ?
8368  ABIArgInfo::getDirectInReg(Result) :
8369  ABIArgInfo::getDirect(Result, 0, nullptr, false);
8370  }
8371 
8372  return Ty->isPromotableIntegerType() ?
8373  (FreeRegs >= SizeInRegs ? ABIArgInfo::getExtendInReg(Ty) :
8374  ABIArgInfo::getExtend(Ty)) :
8375  (FreeRegs >= SizeInRegs ? ABIArgInfo::getDirectInReg() :
8377 }
8378 
8380  if (RetTy->isAnyComplexType())
8381  return ABIArgInfo::getDirectInReg();
8382 
8383  // Arguments of size > 4 registers are indirect.
8384  auto RetSize = llvm::alignTo(getContext().getTypeSize(RetTy), 32) / 32;
8385  if (RetSize > 4)
8386  return getIndirectByRef(RetTy, /*HasFreeRegs*/ true);
8387 
8388  return DefaultABIInfo::classifyReturnType(RetTy);
8389 }
8390 
8391 } // End anonymous namespace.
8392 
8393 //===----------------------------------------------------------------------===//
8394 // XCore ABI Implementation
8395 //===----------------------------------------------------------------------===//
8396 
8397 namespace {
8398 
8399 /// A SmallStringEnc instance is used to build up the TypeString by passing
8400 /// it by reference between functions that append to it.
8401 typedef llvm::SmallString<128> SmallStringEnc;
8402 
8403 /// TypeStringCache caches the meta encodings of Types.
8404 ///
8405 /// The reason for caching TypeStrings is two fold:
8406 /// 1. To cache a type's encoding for later uses;
8407 /// 2. As a means to break recursive member type inclusion.
8408 ///
8409 /// A cache Entry can have a Status of:
8410 /// NonRecursive: The type encoding is not recursive;
8411 /// Recursive: The type encoding is recursive;
8412 /// Incomplete: An incomplete TypeString;
8413 /// IncompleteUsed: An incomplete TypeString that has been used in a
8414 /// Recursive type encoding.
8415 ///
8416 /// A NonRecursive entry will have all of its sub-members expanded as fully
8417 /// as possible. Whilst it may contain types which are recursive, the type
8418 /// itself is not recursive and thus its encoding may be safely used whenever
8419 /// the type is encountered.
8420 ///
8421 /// A Recursive entry will have all of its sub-members expanded as fully as
8422 /// possible. The type itself is recursive and it may contain other types which
8423 /// are recursive. The Recursive encoding must not be used during the expansion
8424 /// of a recursive type's recursive branch. For simplicity the code uses
8425 /// IncompleteCount to reject all usage of Recursive encodings for member types.
8426 ///
8427 /// An Incomplete entry is always a RecordType and only encodes its
8428 /// identifier e.g. "s(S){}". Incomplete 'StubEnc' entries are ephemeral and
8429 /// are placed into the cache during type expansion as a means to identify and
8430 /// handle recursive inclusion of types as sub-members. If there is recursion
8431 /// the entry becomes IncompleteUsed.
8432 ///
8433 /// During the expansion of a RecordType's members:
8434 ///
8435 /// If the cache contains a NonRecursive encoding for the member type, the
8436 /// cached encoding is used;
8437 ///
8438 /// If the cache contains a Recursive encoding for the member type, the
8439 /// cached encoding is 'Swapped' out, as it may be incorrect, and...
8440 ///
8441 /// If the member is a RecordType, an Incomplete encoding is placed into the
8442 /// cache to break potential recursive inclusion of itself as a sub-member;
8443 ///
8444 /// Once a member RecordType has been expanded, its temporary incomplete
8445 /// entry is removed from the cache. If a Recursive encoding was swapped out
8446 /// it is swapped back in;
8447 ///
8448 /// If an incomplete entry is used to expand a sub-member, the incomplete
8449 /// entry is marked as IncompleteUsed. The cache keeps count of how many
8450 /// IncompleteUsed entries it currently contains in IncompleteUsedCount;
8451 ///
8452 /// If a member's encoding is found to be a NonRecursive or Recursive viz:
8453 /// IncompleteUsedCount==0, the member's encoding is added to the cache.
8454 /// Else the member is part of a recursive type and thus the recursion has
8455 /// been exited too soon for the encoding to be correct for the member.
8456 ///
8457 class TypeStringCache {
8458  enum Status {NonRecursive, Recursive, Incomplete, IncompleteUsed};
8459  struct Entry {
8460  std::string Str; // The encoded TypeString for the type.
8461  enum Status State; // Information about the encoding in 'Str'.
8462  std::string Swapped; // A temporary place holder for a Recursive encoding
8463  // during the expansion of RecordType's members.
8464  };
8465  std::map<const IdentifierInfo *, struct Entry> Map;
8466  unsigned IncompleteCount; // Number of Incomplete entries in the Map.
8467  unsigned IncompleteUsedCount; // Number of IncompleteUsed entries in the Map.
8468 public:
8469  TypeStringCache() : IncompleteCount(0), IncompleteUsedCount(0) {}
8470  void addIncomplete(const IdentifierInfo *ID, std::string StubEnc);
8471  bool removeIncomplete(const IdentifierInfo *ID);
8472  void addIfComplete(const IdentifierInfo *ID, StringRef Str,
8473  bool IsRecursive);
8474  StringRef lookupStr(const IdentifierInfo *ID);
8475 };
8476 
8477 /// TypeString encodings for enum & union fields must be order.
8478 /// FieldEncoding is a helper for this ordering process.
8479 class FieldEncoding {
8480  bool HasName;
8481  std::string Enc;
8482 public:
8483  FieldEncoding(bool b, SmallStringEnc &e) : HasName(b), Enc(e.c_str()) {}
8484  StringRef str() { return Enc; }
8485  bool operator<(const FieldEncoding &rhs) const {
8486  if (HasName != rhs.HasName) return HasName;
8487  return Enc < rhs.Enc;
8488  }
8489 };
8490 
8491 class XCoreABIInfo : public DefaultABIInfo {
8492 public:
8493  XCoreABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
8494  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8495  QualType Ty) const override;
8496 };
8497 
8498 class XCoreTargetCodeGenInfo : public TargetCodeGenInfo {
8499  mutable TypeStringCache TSC;
8500 public:
8501  XCoreTargetCodeGenInfo(CodeGenTypes &CGT)
8502  :TargetCodeGenInfo(new XCoreABIInfo(CGT)) {}
8503  void emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8504  CodeGen::CodeGenModule &M) const override;
8505 };
8506 
8507 } // End anonymous namespace.
8508 
8509 // TODO: this implementation is likely now redundant with the default
8510 // EmitVAArg.
8511 Address XCoreABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
8512  QualType Ty) const {
8513  CGBuilderTy &Builder = CGF.Builder;
8514 
8515  // Get the VAList.
8516  CharUnits SlotSize = CharUnits::fromQuantity(4);
8517  Address AP(Builder.CreateLoad(VAListAddr), SlotSize);
8518 
8519  // Handle the argument.
8521  CharUnits TypeAlign = getContext().getTypeAlignInChars(Ty);
8522  llvm::Type *ArgTy = CGT.ConvertType(Ty);
8523  if (AI.canHaveCoerceToType() && !AI.getCoerceToType())
8524  AI.setCoerceToType(ArgTy);
8525  llvm::Type *ArgPtrTy = llvm::PointerType::getUnqual(ArgTy);
8526 
8527  Address Val = Address::invalid();
8528  CharUnits ArgSize = CharUnits::Zero();
8529  switch (AI.getKind()) {
8530  case ABIArgInfo::Expand:
8532  case ABIArgInfo::InAlloca:
8533  llvm_unreachable("Unsupported ABI kind for va_arg");
8534  case ABIArgInfo::Ignore:
8535  Val = Address(llvm::UndefValue::get(ArgPtrTy), TypeAlign);
8536  ArgSize = CharUnits::Zero();
8537  break;
8538  case ABIArgInfo::Extend:
8539  case ABIArgInfo::Direct:
8540  Val = Builder.CreateBitCast(AP, ArgPtrTy);
8541  ArgSize = CharUnits::fromQuantity(
8542  getDataLayout().getTypeAllocSize(AI.getCoerceToType()));
8543  ArgSize = ArgSize.alignTo(SlotSize);
8544  break;
8545  case ABIArgInfo::Indirect:
8546  Val = Builder.CreateElementBitCast(AP, ArgPtrTy);
8547  Val = Address(Builder.CreateLoad(Val), TypeAlign);
8548  ArgSize = SlotSize;
8549  break;
8550  }
8551 
8552  // Increment the VAList.
8553  if (!ArgSize.isZero()) {
8554  llvm::Value *APN =
8555  Builder.CreateConstInBoundsByteGEP(AP.getPointer(), ArgSize);
8556  Builder.CreateStore(APN, VAListAddr);
8557  }
8558 
8559  return Val;
8560 }
8561 
8562 /// During the expansion of a RecordType, an incomplete TypeString is placed
8563 /// into the cache as a means to identify and break recursion.
8564 /// If there is a Recursive encoding in the cache, it is swapped out and will
8565 /// be reinserted by removeIncomplete().
8566 /// All other types of encoding should have been used rather than arriving here.
8567 void TypeStringCache::addIncomplete(const IdentifierInfo *ID,
8568  std::string StubEnc) {
8569  if (!ID)
8570  return;
8571  Entry &E = Map[ID];
8572  assert( (E.Str.empty() || E.State == Recursive) &&
8573  "Incorrectly use of addIncomplete");
8574  assert(!StubEnc.empty() && "Passing an empty string to addIncomplete()");
8575  E.Swapped.swap(E.Str); // swap out the Recursive
8576  E.Str.swap(StubEnc);
8577  E.State = Incomplete;
8578  ++IncompleteCount;
8579 }
8580 
8581 /// Once the RecordType has been expanded, the temporary incomplete TypeString
8582 /// must be removed from the cache.
8583 /// If a Recursive was swapped out by addIncomplete(), it will be replaced.
8584 /// Returns true if the RecordType was defined recursively.
8585 bool TypeStringCache::removeIncomplete(const IdentifierInfo *ID) {
8586  if (!ID)
8587  return false;
8588  auto I = Map.find(ID);
8589  assert(I != Map.end() && "Entry not present");
8590  Entry &E = I->second;
8591  assert( (E.State == Incomplete ||
8592  E.State == IncompleteUsed) &&
8593  "Entry must be an incomplete type");
8594  bool IsRecursive = false;
8595  if (E.State == IncompleteUsed) {
8596  // We made use of our Incomplete encoding, thus we are recursive.
8597  IsRecursive = true;
8598  --IncompleteUsedCount;
8599  }
8600  if (E.Swapped.empty())
8601  Map.erase(I);
8602  else {
8603  // Swap the Recursive back.
8604  E.Swapped.swap(E.Str);
8605  E.Swapped.clear();
8606  E.State = Recursive;
8607  }
8608  --IncompleteCount;
8609  return IsRecursive;
8610 }
8611 
8612 /// Add the encoded TypeString to the cache only if it is NonRecursive or
8613 /// Recursive (viz: all sub-members were expanded as fully as possible).
8614 void TypeStringCache::addIfComplete(const IdentifierInfo *ID, StringRef Str,
8615  bool IsRecursive) {
8616  if (!ID || IncompleteUsedCount)
8617  return; // No key or it is is an incomplete sub-type so don't add.
8618  Entry &E = Map[ID];
8619  if (IsRecursive && !E.Str.empty()) {
8620  assert(E.State==Recursive && E.Str.size() == Str.size() &&
8621  "This is not the same Recursive entry");
8622  // The parent container was not recursive after all, so we could have used
8623  // this Recursive sub-member entry after all, but we assumed the worse when
8624  // we started viz: IncompleteCount!=0.
8625  return;
8626  }
8627  assert(E.Str.empty() && "Entry already present");
8628  E.Str = Str.str();
8629  E.State = IsRecursive? Recursive : NonRecursive;
8630 }
8631 
8632 /// Return a cached TypeString encoding for the ID. If there isn't one, or we
8633 /// are recursively expanding a type (IncompleteCount != 0) and the cached
8634 /// encoding is Recursive, return an empty StringRef.
8635 StringRef TypeStringCache::lookupStr(const IdentifierInfo *ID) {
8636  if (!ID)
8637  return StringRef(); // We have no key.
8638  auto I = Map.find(ID);
8639  if (I == Map.end())
8640  return StringRef(); // We have no encoding.
8641  Entry &E = I->second;
8642  if (E.State == Recursive && IncompleteCount)
8643  return StringRef(); // We don't use Recursive encodings for member types.
8644 
8645  if (E.State == Incomplete) {
8646  // The incomplete type is being used to break out of recursion.
8647  E.State = IncompleteUsed;
8648  ++IncompleteUsedCount;
8649  }
8650  return E.Str;
8651 }
8652 
8653 /// The XCore ABI includes a type information section that communicates symbol
8654 /// type information to the linker. The linker uses this information to verify
8655 /// safety/correctness of things such as array bound and pointers et al.
8656 /// The ABI only requires C (and XC) language modules to emit TypeStrings.
8657 /// This type information (TypeString) is emitted into meta data for all global
8658 /// symbols: definitions, declarations, functions & variables.
8659 ///
8660 /// The TypeString carries type, qualifier, name, size & value details.
8661 /// Please see 'Tools Development Guide' section 2.16.2 for format details:
8662 /// https://www.xmos.com/download/public/Tools-Development-Guide%28X9114A%29.pdf
8663 /// The output is tested by test/CodeGen/xcore-stringtype.c.
8664 ///
8665 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
8666  CodeGen::CodeGenModule &CGM, TypeStringCache &TSC);
8667 
8668 /// XCore uses emitTargetMD to emit TypeString metadata for global symbols.
8669 void XCoreTargetCodeGenInfo::emitTargetMD(const Decl *D, llvm::GlobalValue *GV,
8670  CodeGen::CodeGenModule &CGM) const {
8671  SmallStringEnc Enc;
8672  if (getTypeString(Enc, D, CGM, TSC)) {
8673  llvm::LLVMContext &Ctx = CGM.getModule().getContext();
8674  llvm::Metadata *MDVals[] = {llvm::ConstantAsMetadata::get(GV),
8675  llvm::MDString::get(Ctx, Enc.str())};
8676  llvm::NamedMDNode *MD =
8677  CGM.getModule().getOrInsertNamedMetadata("xcore.typestrings");
8678  MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
8679  }
8680 }
8681 
8682 //===----------------------------------------------------------------------===//
8683 // SPIR ABI Implementation
8684 //===----------------------------------------------------------------------===//
8685 
8686 namespace {
8687 class SPIRTargetCodeGenInfo : public TargetCodeGenInfo {
8688 public:
8689  SPIRTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
8690  : TargetCodeGenInfo(new DefaultABIInfo(CGT)) {}
8691  unsigned getOpenCLKernelCallingConv() const override;
8692 };
8693 
8694 } // End anonymous namespace.
8695 
8696 namespace clang {
8697 namespace CodeGen {
8699  DefaultABIInfo SPIRABI(CGM.getTypes());
8700  SPIRABI.computeInfo(FI);
8701 }
8702 }
8703 }
8704 
8705 unsigned SPIRTargetCodeGenInfo::getOpenCLKernelCallingConv() const {
8706  return llvm::CallingConv::SPIR_KERNEL;
8707 }
8708 
8709 static bool appendType(SmallStringEnc &Enc, QualType QType,
8710  const CodeGen::CodeGenModule &CGM,
8711  TypeStringCache &TSC);
8712 
8713 /// Helper function for appendRecordType().
8714 /// Builds a SmallVector containing the encoded field types in declaration
8715 /// order.
8717  const RecordDecl *RD,
8718  const CodeGen::CodeGenModule &CGM,
8719  TypeStringCache &TSC) {
8720  for (const auto *Field : RD->fields()) {
8721  SmallStringEnc Enc;
8722  Enc += "m(";
8723  Enc += Field->getName();
8724  Enc += "){";
8725  if (Field->isBitField()) {
8726  Enc += "b(";
8727  llvm::raw_svector_ostream OS(Enc);
8728  OS << Field->getBitWidthValue(CGM.getContext());
8729  Enc += ':';
8730  }
8731  if (!appendType(Enc, Field->getType(), CGM, TSC))
8732  return false;
8733  if (Field->isBitField())
8734  Enc += ')';
8735  Enc += '}';
8736  FE.emplace_back(!Field->getName().empty(), Enc);
8737  }
8738  return true;
8739 }
8740 
8741 /// Appends structure and union types to Enc and adds encoding to cache.
8742 /// Recursively calls appendType (via extractFieldType) for each field.
8743 /// Union types have their fields ordered according to the ABI.
8744 static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT,
8745  const CodeGen::CodeGenModule &CGM,
8746  TypeStringCache &TSC, const IdentifierInfo *ID) {
8747  // Append the cached TypeString if we have one.
8748  StringRef TypeString = TSC.lookupStr(ID);
8749  if (!TypeString.empty()) {
8750  Enc += TypeString;
8751  return true;
8752  }
8753 
8754  // Start to emit an incomplete TypeString.
8755  size_t Start = Enc.size();
8756  Enc += (RT->isUnionType()? 'u' : 's');
8757  Enc += '(';
8758  if (ID)
8759  Enc += ID->getName();
8760  Enc += "){";
8761 
8762  // We collect all encoded fields and order as necessary.
8763  bool IsRecursive = false;
8764  const RecordDecl *RD = RT->getDecl()->getDefinition();
8765  if (RD && !RD->field_empty()) {
8766  // An incomplete TypeString stub is placed in the cache for this RecordType
8767  // so that recursive calls to this RecordType will use it whilst building a
8768  // complete TypeString for this RecordType.
8770  std::string StubEnc(Enc.substr(Start).str());
8771  StubEnc += '}'; // StubEnc now holds a valid incomplete TypeString.
8772  TSC.addIncomplete(ID, std::move(StubEnc));
8773  if (!extractFieldType(FE, RD, CGM, TSC)) {
8774  (void) TSC.removeIncomplete(ID);
8775  return false;
8776  }
8777  IsRecursive = TSC.removeIncomplete(ID);
8778  // The ABI requires unions to be sorted but not structures.
8779  // See FieldEncoding::operator< for sort algorithm.
8780  if (RT->isUnionType())
8781  llvm::sort(FE);
8782  // We can now complete the TypeString.
8783  unsigned E = FE.size();
8784  for (unsigned I = 0; I != E; ++I) {
8785  if (I)
8786  Enc += ',';
8787  Enc += FE[I].str();
8788  }
8789  }
8790  Enc += '}';
8791  TSC.addIfComplete(ID, Enc.substr(Start), IsRecursive);
8792  return true;
8793 }
8794 
8795 /// Appends enum types to Enc and adds the encoding to the cache.
8796 static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET,
8797  TypeStringCache &TSC,
8798  const IdentifierInfo *ID) {
8799  // Append the cached TypeString if we have one.
8800  StringRef TypeString = TSC.lookupStr(ID);
8801  if (!TypeString.empty()) {
8802  Enc += TypeString;
8803  return true;
8804  }
8805 
8806  size_t Start = Enc.size();
8807  Enc += "e(";
8808  if (ID)
8809  Enc += ID->getName();
8810  Enc += "){";
8811 
8812  // We collect all encoded enumerations and order them alphanumerically.
8813  if (const EnumDecl *ED = ET->getDecl()->getDefinition()) {
8815  for (auto I = ED->enumerator_begin(), E = ED->enumerator_end(); I != E;
8816  ++I) {
8817  SmallStringEnc EnumEnc;
8818  EnumEnc += "m(";
8819  EnumEnc += I->getName();
8820  EnumEnc += "){";
8821  I->getInitVal().toString(EnumEnc);
8822  EnumEnc += '}';
8823  FE.push_back(FieldEncoding(!I->getName().empty(), EnumEnc));
8824  }
8825  llvm::sort(FE);
8826  unsigned E = FE.size();
8827  for (unsigned I = 0; I != E; ++I) {
8828  if (I)
8829  Enc += ',';
8830  Enc += FE[I].str();
8831  }
8832  }
8833  Enc += '}';
8834  TSC.addIfComplete(ID, Enc.substr(Start), false);
8835  return true;
8836 }
8837 
8838 /// Appends type's qualifier to Enc.
8839 /// This is done prior to appending the type's encoding.
8840 static void appendQualifier(SmallStringEnc &Enc, QualType QT) {
8841  // Qualifiers are emitted in alphabetical order.
8842  static const char *const Table[]={"","c:","r:","cr:","v:","cv:","rv:","crv:"};
8843  int Lookup = 0;
8844  if (QT.isConstQualified())
8845  Lookup += 1<<0;
8846  if (QT.isRestrictQualified())
8847  Lookup += 1<<1;
8848  if (QT.isVolatileQualified())
8849  Lookup += 1<<2;
8850  Enc += Table[Lookup];
8851 }
8852 
8853 /// Appends built-in types to Enc.
8854 static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT) {
8855  const char *EncType;
8856  switch (BT->getKind()) {
8857  case BuiltinType::Void:
8858  EncType = "0";
8859  break;
8860  case BuiltinType::Bool:
8861  EncType = "b";
8862  break;
8863  case BuiltinType::Char_U:
8864  EncType = "uc";
8865  break;
8866  case BuiltinType::UChar:
8867  EncType = "uc";
8868  break;
8869  case BuiltinType::SChar:
8870  EncType = "sc";
8871  break;
8872  case BuiltinType::UShort:
8873  EncType = "us";
8874  break;
8875  case BuiltinType::Short:
8876  EncType = "ss";
8877  break;
8878  case BuiltinType::UInt:
8879  EncType = "ui";
8880  break;
8881  case BuiltinType::Int:
8882  EncType = "si";
8883  break;
8884  case BuiltinType::ULong:
8885  EncType = "ul";
8886  break;
8887  case BuiltinType::Long:
8888  EncType = "sl";
8889  break;
8890  case BuiltinType::ULongLong:
8891  EncType = "ull";
8892  break;
8893  case BuiltinType::LongLong:
8894  EncType = "sll";
8895  break;
8896  case BuiltinType::Float:
8897  EncType = "ft";
8898  break;
8899  case BuiltinType::Double:
8900  EncType = "d";
8901  break;
8902  case BuiltinType::LongDouble:
8903  EncType = "ld";
8904  break;
8905  default:
8906  return false;
8907  }
8908  Enc += EncType;
8909  return true;
8910 }
8911 
8912 /// Appends a pointer encoding to Enc before calling appendType for the pointee.
8913 static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT,
8914  const CodeGen::CodeGenModule &CGM,
8915  TypeStringCache &TSC) {
8916  Enc += "p(";
8917  if (!appendType(Enc, PT->getPointeeType(), CGM, TSC))
8918  return false;
8919  Enc += ')';
8920  return true;
8921 }
8922 
8923 /// Appends array encoding to Enc before calling appendType for the element.
8924 static bool appendArrayType(SmallStringEnc &Enc, QualType QT,
8925  const ArrayType *AT,
8926  const CodeGen::CodeGenModule &CGM,
8927  TypeStringCache &TSC, StringRef NoSizeEnc) {
8928  if (AT->getSizeModifier() != ArrayType::Normal)
8929  return false;
8930  Enc += "a(";
8931  if (const ConstantArrayType *CAT = dyn_cast<ConstantArrayType>(AT))
8932  CAT->getSize().toStringUnsigned(Enc);
8933  else
8934  Enc += NoSizeEnc; // Global arrays use "*", otherwise it is "".
8935  Enc += ':';
8936  // The Qualifiers should be attached to the type rather than the array.
8937  appendQualifier(Enc, QT);
8938  if (!appendType(Enc, AT->getElementType(), CGM, TSC))
8939  return false;
8940  Enc += ')';
8941  return true;
8942 }
8943 
8944 /// Appends a function encoding to Enc, calling appendType for the return type
8945 /// and the arguments.
8946 static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT,
8947  const CodeGen::CodeGenModule &CGM,
8948  TypeStringCache &TSC) {
8949  Enc += "f{";
8950  if (!appendType(Enc, FT->getReturnType(), CGM, TSC))
8951  return false;
8952  Enc += "}(";
8953  if (const FunctionProtoType *FPT = FT->getAs<FunctionProtoType>()) {
8954  // N.B. we are only interested in the adjusted param types.
8955  auto I = FPT->param_type_begin();
8956  auto E = FPT->param_type_end();
8957  if (I != E) {
8958  do {
8959  if (!appendType(Enc, *I, CGM, TSC))
8960  return false;
8961  ++I;
8962  if (I != E)
8963  Enc += ',';
8964  } while (I != E);
8965  if (FPT->isVariadic())
8966  Enc += ",va";
8967  } else {
8968  if (FPT->isVariadic())
8969  Enc += "va";
8970  else
8971  Enc += '0';
8972  }
8973  }
8974  Enc += ')';
8975  return true;
8976 }
8977 
8978 /// Handles the type's qualifier before dispatching a call to handle specific
8979 /// type encodings.
8980 static bool appendType(SmallStringEnc &Enc, QualType QType,
8981  const CodeGen::CodeGenModule &CGM,
8982  TypeStringCache &TSC) {
8983 
8984  QualType QT = QType.getCanonicalType();
8985 
8986  if (const ArrayType *AT = QT->getAsArrayTypeUnsafe())
8987  // The Qualifiers should be attached to the type rather than the array.
8988  // Thus we don't call appendQualifier() here.
8989  return appendArrayType(Enc, QT, AT, CGM, TSC, "");
8990 
8991  appendQualifier(Enc, QT);
8992 
8993  if (const BuiltinType *BT = QT->getAs<BuiltinType>())
8994  return appendBuiltinType(Enc, BT);
8995 
8996  if (const PointerType *PT = QT->getAs<PointerType>())
8997  return appendPointerType(Enc, PT, CGM, TSC);
8998 
8999  if (const EnumType *ET = QT->getAs<EnumType>())
9000  return appendEnumType(Enc, ET, TSC, QT.getBaseTypeIdentifier());
9001 
9002  if (const RecordType *RT = QT->getAsStructureType())
9003  return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
9004 
9005  if (const RecordType *RT = QT->getAsUnionType())
9006  return appendRecordType(Enc, RT, CGM, TSC, QT.getBaseTypeIdentifier());
9007 
9008  if (const FunctionType *FT = QT->getAs<FunctionType>())
9009  return appendFunctionType(Enc, FT, CGM, TSC);
9010 
9011  return false;
9012 }
9013 
9014 static bool getTypeString(SmallStringEnc &Enc, const Decl *D,
9015  CodeGen::CodeGenModule &CGM, TypeStringCache &TSC) {
9016  if (!D)
9017  return false;
9018 
9019  if (const FunctionDecl *FD = dyn_cast<FunctionDecl>(D)) {
9020  if (FD->getLanguageLinkage() != CLanguageLinkage)
9021  return false;
9022  return appendType(Enc, FD->getType(), CGM, TSC);
9023  }
9024 
9025  if (const VarDecl *VD = dyn_cast<VarDecl>(D)) {
9026  if (VD->getLanguageLinkage() != CLanguageLinkage)
9027  return false;
9028  QualType QT = VD->getType().getCanonicalType();
9029  if (const ArrayType *AT = QT->getAsArrayTypeUnsafe()) {
9030  // Global ArrayTypes are given a size of '*' if the size is unknown.
9031  // The Qualifiers should be attached to the type rather than the array.
9032  // Thus we don't call appendQualifier() here.
9033  return appendArrayType(Enc, QT, AT, CGM, TSC, "*");
9034  }
9035  return appendType(Enc, QT, CGM, TSC);
9036  }
9037  return false;
9038 }
9039 
9040 //===----------------------------------------------------------------------===//
9041 // RISCV ABI Implementation
9042 //===----------------------------------------------------------------------===//
9043 
9044 namespace {
9045 class RISCVABIInfo : public DefaultABIInfo {
9046 private:
9047  unsigned XLen; // Size of the integer ('x') registers in bits.
9048  static const int NumArgGPRs = 8;
9049 
9050 public:
9051  RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
9052  : DefaultABIInfo(CGT), XLen(XLen) {}
9053 
9054  // DefaultABIInfo's classifyReturnType and classifyArgumentType are
9055  // non-virtual, but computeInfo is virtual, so we overload it.
9056  void computeInfo(CGFunctionInfo &FI) const override;
9057 
9058  ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed,
9059  int &ArgGPRsLeft) const;
9060  ABIArgInfo classifyReturnType(QualType RetTy) const;
9061 
9062  Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
9063  QualType Ty) const override;
9064 
9065  ABIArgInfo extendType(QualType Ty) const;
9066 };
9067 } // end anonymous namespace
9068 
9069 void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
9070  QualType RetTy = FI.getReturnType();
9071  if (!getCXXABI().classifyReturnType(FI))
9072  FI.getReturnInfo() = classifyReturnType(RetTy);
9073 
9074  // IsRetIndirect is true if classifyArgumentType indicated the value should
9075  // be passed indirect or if the type size is greater than 2*xlen. e.g. fp128
9076  // is passed direct in LLVM IR, relying on the backend lowering code to
9077  // rewrite the argument list and pass indirectly on RV32.
9078  bool IsRetIndirect = FI.getReturnInfo().getKind() == ABIArgInfo::Indirect ||
9079  getContext().getTypeSize(RetTy) > (2 * XLen);
9080 
9081  // We must track the number of GPRs used in order to conform to the RISC-V
9082  // ABI, as integer scalars passed in registers should have signext/zeroext
9083  // when promoted, but are anyext if passed on the stack. As GPR usage is
9084  // different for variadic arguments, we must also track whether we are
9085  // examining a vararg or not.
9086  int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs;
9087  int NumFixedArgs = FI.getNumRequiredArgs();
9088 
9089  int ArgNum = 0;
9090  for (auto &ArgInfo : FI.arguments()) {
9091  bool IsFixed = ArgNum < NumFixedArgs;
9092  ArgInfo.info = classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft);
9093  ArgNum++;
9094  }
9095 }
9096 
9098  int &ArgGPRsLeft) const {
9099  assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
9101 
9102  // Structures with either a non-trivial destructor or a non-trivial
9103  // copy constructor are always passed indirectly.
9105  if (ArgGPRsLeft)
9106  ArgGPRsLeft -= 1;
9107  return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
9109  }
9110 
9111  // Ignore empty structs/unions.
9112  if (isEmptyRecord(getContext(), Ty, true))
9113  return ABIArgInfo::getIgnore();
9114 
9115  uint64_t Size = getContext().getTypeSize(Ty);
9116  uint64_t NeededAlign = getContext().getTypeAlign(Ty);
9117  bool MustUseStack = false;
9118  // Determine the number of GPRs needed to pass the current argument
9119  // according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
9120  // register pairs, so may consume 3 registers.
9121  int NeededArgGPRs = 1;
9122  if (!IsFixed && NeededAlign == 2 * XLen)
9123  NeededArgGPRs = 2 + (ArgGPRsLeft % 2);
9124  else if (Size > XLen && Size <= 2 * XLen)
9125  NeededArgGPRs = 2;
9126 
9127  if (NeededArgGPRs > ArgGPRsLeft) {
9128  MustUseStack = true;
9129  NeededArgGPRs = ArgGPRsLeft;
9130  }
9131 
9132  ArgGPRsLeft -= NeededArgGPRs;
9133 
9134  if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType()) {
9135  // Treat an enum type as its underlying type.
9136  if (const EnumType *EnumTy = Ty->getAs<EnumType>())
9137  Ty = EnumTy->getDecl()->getIntegerType();
9138 
9139  // All integral types are promoted to XLen width, unless passed on the
9140  // stack.
9141  if (Size < XLen && Ty->isIntegralOrEnumerationType() && !MustUseStack) {
9142  return extendType(Ty);
9143  }
9144 
9145  return ABIArgInfo::getDirect();
9146  }
9147 
9148  // Aggregates which are <= 2*XLen will be passed in registers if possible,
9149  // so coerce to integers.
9150  if (Size <= 2 * XLen) {
9151  unsigned Alignment = getContext().getTypeAlign(Ty);
9152 
9153  // Use a single XLen int if possible, 2*XLen if 2*XLen alignment is
9154  // required, and a 2-element XLen array if only XLen alignment is required.
9155  if (Size <= XLen) {
9156  return ABIArgInfo::getDirect(
9157  llvm::IntegerType::get(getVMContext(), XLen));
9158  } else if (Alignment == 2 * XLen) {
9159  return ABIArgInfo::getDirect(
9160  llvm::IntegerType::get(getVMContext(), 2 * XLen));
9161  } else {
9162  return ABIArgInfo::getDirect(llvm::ArrayType::get(
9163  llvm::IntegerType::get(getVMContext(), XLen), 2));
9164  }
9165  }
9166  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
9167 }
9168 
9170  if (RetTy->isVoidType())
9171  return ABIArgInfo::getIgnore();
9172 
9173  int ArgGPRsLeft = 2;
9174 
9175  // The rules for return and argument types are the same, so defer to
9176  // classifyArgumentType.
9177  return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft);
9178 }
9179 
9180 Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
9181  QualType Ty) const {
9182  CharUnits SlotSize = CharUnits::fromQuantity(XLen / 8);
9183 
9184  // Empty records are ignored for parameter passing purposes.
9185  if (isEmptyRecord(getContext(), Ty, true)) {
9186  Address Addr(CGF.Builder.CreateLoad(VAListAddr), SlotSize);
9187  Addr = CGF.Builder.CreateElementBitCast(Addr, CGF.ConvertTypeForMem(Ty));
9188  return Addr;
9189  }
9190 
9191  std::pair<CharUnits, CharUnits> SizeAndAlign =
9193 
9194  // Arguments bigger than 2*Xlen bytes are passed indirectly.
9195  bool IsIndirect = SizeAndAlign.first > 2 * SlotSize;
9196 
9197  return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, SizeAndAlign,
9198  SlotSize, /*AllowHigherAlign=*/true);
9199 }
9200 
9201 ABIArgInfo RISCVABIInfo::extendType(QualType Ty) const {
9202  int TySize = getContext().getTypeSize(Ty);
9203  // RV64 ABI requires unsigned 32 bit integers to be sign extended.
9204  if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
9205  return ABIArgInfo::getSignExtend(Ty);
9206  return ABIArgInfo::getExtend(Ty);
9207 }
9208 
9209 namespace {
9210 class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
9211 public:
9212  RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen)
9213  : TargetCodeGenInfo(new RISCVABIInfo(CGT, XLen)) {}
9214 
9215  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
9216  CodeGen::CodeGenModule &CGM) const override {
9217  const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
9218  if (!FD) return;
9219 
9220  const auto *Attr = FD->getAttr<RISCVInterruptAttr>();
9221  if (!Attr)
9222  return;
9223 
9224  const char *Kind;
9225  switch (Attr->getInterrupt()) {
9226  case RISCVInterruptAttr::user: Kind = "user"; break;
9227  case RISCVInterruptAttr::supervisor: Kind = "supervisor"; break;
9228  case RISCVInterruptAttr::machine: Kind = "machine"; break;
9229  }
9230 
9231  auto *Fn = cast<llvm::Function>(GV);
9232 
9233  Fn->addFnAttr("interrupt", Kind);
9234  }
9235 };
9236 } // namespace
9237 
9238 //===----------------------------------------------------------------------===//
9239 // Driver code
9240 //===----------------------------------------------------------------------===//
9241 
9243  return getTriple().supportsCOMDAT();
9244 }
9245 
9247  if (TheTargetCodeGenInfo)
9248  return *TheTargetCodeGenInfo;
9249 
9250  // Helper to set the unique_ptr while still keeping the return value.
9251  auto SetCGInfo = [&](TargetCodeGenInfo *P) -> const TargetCodeGenInfo & {
9252  this->TheTargetCodeGenInfo.reset(P);
9253  return *P;
9254  };
9255 
9256  const llvm::Triple &Triple = getTarget().getTriple();
9257  switch (Triple.getArch()) {
9258  default:
9259  return SetCGInfo(new DefaultTargetCodeGenInfo(Types));
9260 
9261  case llvm::Triple::le32:
9262  return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9263  case llvm::Triple::mips:
9264  case llvm::Triple::mipsel:
9265  if (Triple.getOS() == llvm::Triple::NaCl)
9266  return SetCGInfo(new PNaClTargetCodeGenInfo(Types));
9267  return SetCGInfo(new MIPSTargetCodeGenInfo(Types, true));
9268 
9269  case llvm::Triple::mips64:
9270  case llvm::Triple::mips64el:
9271  return SetCGInfo(new MIPSTargetCodeGenInfo(Types, false));
9272 
9273  case llvm::Triple::avr:
9274  return SetCGInfo(new AVRTargetCodeGenInfo(Types));
9275 
9276  case llvm::Triple::aarch64:
9277  case llvm::Triple::aarch64_be: {
9278  AArch64ABIInfo::ABIKind Kind = AArch64ABIInfo::AAPCS;
9279  if (getTarget().getABI() == "darwinpcs")
9280  Kind = AArch64ABIInfo::DarwinPCS;
9281  else if (Triple.isOSWindows())
9282  return SetCGInfo(
9283  new WindowsAArch64TargetCodeGenInfo(Types, AArch64ABIInfo::Win64));
9284 
9285  return SetCGInfo(new AArch64TargetCodeGenInfo(Types, Kind));
9286  }
9287 
9288  case llvm::Triple::wasm32:
9289  case llvm::Triple::wasm64:
9290  return SetCGInfo(new WebAssemblyTargetCodeGenInfo(Types));
9291 
9292  case llvm::Triple::arm:
9293  case llvm::Triple::armeb:
9294  case llvm::Triple::thumb:
9295  case llvm::Triple::thumbeb: {
9296  if (Triple.getOS() == llvm::Triple::Win32) {
9297  return SetCGInfo(
9298  new WindowsARMTargetCodeGenInfo(Types, ARMABIInfo::AAPCS_VFP));
9299  }
9300 
9301  ARMABIInfo::ABIKind Kind = ARMABIInfo::AAPCS;
9302  StringRef ABIStr = getTarget().getABI();
9303  if (ABIStr == "apcs-gnu")
9304  Kind = ARMABIInfo::APCS;
9305  else if (ABIStr == "aapcs16")
9306  Kind = ARMABIInfo::AAPCS16_VFP;
9307  else if (CodeGenOpts.FloatABI == "hard" ||
9308  (CodeGenOpts.FloatABI != "soft" &&
9309  (Triple.getEnvironment() == llvm::Triple::GNUEABIHF ||
9310  Triple.getEnvironment() == llvm::Triple::MuslEABIHF ||
9311  Triple.getEnvironment() == llvm::Triple::EABIHF)))
9312  Kind = ARMABIInfo::AAPCS_VFP;
9313 
9314  return SetCGInfo(new ARMTargetCodeGenInfo(Types, Kind));
9315  }
9316 
9317  case llvm::Triple::ppc:
9318  return SetCGInfo(
9319  new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
9320  case llvm::Triple::ppc64:
9321  if (Triple.isOSBinFormatELF()) {
9322  PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
9323  if (getTarget().getABI() == "elfv2")
9324  Kind = PPC64_SVR4_ABIInfo::ELFv2;
9325  bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9326  bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9327 
9328  return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9329  IsSoftFloat));
9330  } else
9331  return SetCGInfo(new PPC64TargetCodeGenInfo(Types));
9332  case llvm::Triple::ppc64le: {
9333  assert(Triple.isOSBinFormatELF() && "PPC64 LE non-ELF not supported!");
9334  PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv2;
9335  if (getTarget().getABI() == "elfv1" || getTarget().getABI() == "elfv1-qpx")
9336  Kind = PPC64_SVR4_ABIInfo::ELFv1;
9337  bool HasQPX = getTarget().getABI() == "elfv1-qpx";
9338  bool IsSoftFloat = CodeGenOpts.FloatABI == "soft";
9339 
9340  return SetCGInfo(new PPC64_SVR4_TargetCodeGenInfo(Types, Kind, HasQPX,
9341  IsSoftFloat));
9342  }
9343 
9344  case llvm::Triple::nvptx:
9345  case llvm::Triple::nvptx64:
9346  return SetCGInfo(new NVPTXTargetCodeGenInfo(Types));
9347 
9348  case llvm::Triple::msp430:
9349  return SetCGInfo(new MSP430TargetCodeGenInfo(Types));
9350 
9351  case llvm::Triple::riscv32:
9352  return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 32));
9353  case llvm::Triple::riscv64:
9354  return SetCGInfo(new RISCVTargetCodeGenInfo(Types, 64));
9355 
9356  case llvm::Triple::systemz: {
9357  bool HasVector = getTarget().getABI() == "vector";
9358  return SetCGInfo(new SystemZTargetCodeGenInfo(Types, HasVector));
9359  }
9360 
9361  case llvm::Triple::tce:
9362  case llvm::Triple::tcele:
9363  return SetCGInfo(new TCETargetCodeGenInfo(Types));
9364 
9365  case llvm::Triple::x86: {
9366  bool IsDarwinVectorABI = Triple.isOSDarwin();
9367  bool RetSmallStructInRegABI =
9368  X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
9369  bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
9370 
9371  if (Triple.getOS() == llvm::Triple::Win32) {
9372  return SetCGInfo(new WinX86_32TargetCodeGenInfo(
9373  Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9374  IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
9375  } else {
9376  return SetCGInfo(new X86_32TargetCodeGenInfo(
9377  Types, IsDarwinVectorABI, RetSmallStructInRegABI,
9378  IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
9379  CodeGenOpts.FloatABI == "soft"));
9380  }
9381  }
9382 
9383  case llvm::Triple::x86_64: {
9384  StringRef ABI = getTarget().getABI();
9385  X86AVXABILevel AVXLevel =
9386  (ABI == "avx512"
9387  ? X86AVXABILevel::AVX512
9388  : ABI == "avx" ? X86AVXABILevel::AVX : X86AVXABILevel::None);
9389 
9390  switch (Triple.getOS()) {
9391  case llvm::Triple::Win32:
9392  return SetCGInfo(new WinX86_64TargetCodeGenInfo(Types, AVXLevel));
9393  case llvm::Triple::PS4:
9394  return SetCGInfo(new PS4TargetCodeGenInfo(Types, AVXLevel));
9395  default:
9396  return SetCGInfo(new X86_64TargetCodeGenInfo(Types, AVXLevel));
9397  }
9398  }
9399  case llvm::Triple::hexagon:
9400  return SetCGInfo(new HexagonTargetCodeGenInfo(Types));
9401  case llvm::Triple::lanai:
9402  return SetCGInfo(new LanaiTargetCodeGenInfo(Types));
9403  case llvm::Triple::r600:
9404  return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9405  case llvm::Triple::amdgcn:
9406  return SetCGInfo(new AMDGPUTargetCodeGenInfo(Types));
9407  case llvm::Triple::sparc:
9408  return SetCGInfo(new SparcV8TargetCodeGenInfo(Types));
9409  case llvm::Triple::sparcv9:
9410  return SetCGInfo(new SparcV9TargetCodeGenInfo(Types));
9411  case llvm::Triple::xcore:
9412  return SetCGInfo(new XCoreTargetCodeGenInfo(Types));
9413  case llvm::Triple::arc:
9414  return SetCGInfo(new ARCTargetCodeGenInfo(Types));
9415  case llvm::Triple::spir:
9416  case llvm::Triple::spir64:
9417  return SetCGInfo(new SPIRTargetCodeGenInfo(Types));
9418  }
9419 }
9420 
9421 /// Create an OpenCL kernel for an enqueued block.
9422 ///
9423 /// The kernel has the same function type as the block invoke function. Its
9424 /// name is the name of the block invoke function postfixed with "_kernel".
9425 /// It simply calls the block invoke function then returns.
9426 llvm::Function *
9428  llvm::Function *Invoke,
9429  llvm::Value *BlockLiteral) const {
9430  auto *InvokeFT = Invoke->getFunctionType();
9432  for (auto &P : InvokeFT->params())
9433  ArgTys.push_back(P);
9434  auto &C = CGF.getLLVMContext();
9435  std::string Name = Invoke->getName().str() + "_kernel";
9436  auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9438  &CGF.CGM.getModule());
9439  auto IP = CGF.Builder.saveIP();
9440  auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9441  auto &Builder = CGF.Builder;
9442  Builder.SetInsertPoint(BB);
9444  for (auto &A : F->args())
9445  Args.push_back(&A);
9446  Builder.CreateCall(Invoke, Args);
9447  Builder.CreateRetVoid();
9448  Builder.restoreIP(IP);
9449  return F;
9450 }
9451 
9452 /// Create an OpenCL kernel for an enqueued block.
9453 ///
9454 /// The type of the first argument (the block literal) is the struct type
9455 /// of the block literal instead of a pointer type. The first argument
9456 /// (block literal) is passed directly by value to the kernel. The kernel
9457 /// allocates the same type of struct on stack and stores the block literal
9458 /// to it and passes its pointer to the block invoke function. The kernel
9459 /// has "enqueued-block" function attribute and kernel argument metadata.
9460 llvm::Function *AMDGPUTargetCodeGenInfo::createEnqueuedBlockKernel(
9461  CodeGenFunction &CGF, llvm::Function *Invoke,
9462  llvm::Value *BlockLiteral) const {
9463  auto &Builder = CGF.Builder;
9464  auto &C = CGF.getLLVMContext();
9465 
9466  auto *BlockTy = BlockLiteral->getType()->getPointerElementType();
9467  auto *InvokeFT = Invoke->getFunctionType();
9472  llvm::SmallVector<llvm::Metadata *, 8> ArgBaseTypeNames;
9475 
9476  ArgTys.push_back(BlockTy);
9477  ArgTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9478  AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(0)));
9479  ArgBaseTypeNames.push_back(llvm::MDString::get(C, "__block_literal"));
9480  ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9481  AccessQuals.push_back(llvm::MDString::get(C, "none"));
9482  ArgNames.push_back(llvm::MDString::get(C, "block_literal"));
9483  for (unsigned I = 1, E = InvokeFT->getNumParams(); I < E; ++I) {
9484  ArgTys.push_back(InvokeFT->getParamType(I));
9485  ArgTypeNames.push_back(llvm::MDString::get(C, "void*"));
9486  AddressQuals.push_back(llvm::ConstantAsMetadata::get(Builder.getInt32(3)));
9487  AccessQuals.push_back(llvm::MDString::get(C, "none"));
9488  ArgBaseTypeNames.push_back(llvm::MDString::get(C, "void*"));
9489  ArgTypeQuals.push_back(llvm::MDString::get(C, ""));
9490  ArgNames.push_back(
9491  llvm::MDString::get(C, (Twine("local_arg") + Twine(I)).str()));
9492  }
9493  std::string Name = Invoke->getName().str() + "_kernel";
9494  auto *FT = llvm::FunctionType::get(llvm::Type::getVoidTy(C), ArgTys, false);
9496  &CGF.CGM.getModule());
9497  F->addFnAttr("enqueued-block");
9498  auto IP = CGF.Builder.saveIP();
9499  auto *BB = llvm::BasicBlock::Create(C, "entry", F);
9500  Builder.SetInsertPoint(BB);
9501  unsigned BlockAlign = CGF.CGM.getDataLayout().getPrefTypeAlignment(BlockTy);
9502  auto *BlockPtr = Builder.CreateAlloca(BlockTy, nullptr);
9503  BlockPtr->setAlignment(BlockAlign);
9504  Builder.CreateAlignedStore(F->arg_begin(), BlockPtr, BlockAlign);
9505  auto *Cast = Builder.CreatePointerCast(BlockPtr, InvokeFT->getParamType(0));
9507  Args.push_back(Cast);
9508  for (auto I = F->arg_begin() + 1, E = F->arg_end(); I != E; ++I)
9509  Args.push_back(I);
9510  Builder.CreateCall(Invoke, Args);
9511  Builder.CreateRetVoid();
9512  Builder.restoreIP(IP);
9513 
9514  F->setMetadata("kernel_arg_addr_space", llvm::MDNode::get(C, AddressQuals));
9515  F->setMetadata("kernel_arg_access_qual", llvm::MDNode::get(C, AccessQuals));
9516  F->setMetadata("kernel_arg_type", llvm::MDNode::get(C, ArgTypeNames));
9517  F->setMetadata("kernel_arg_base_type",
9518  llvm::MDNode::get(C, ArgBaseTypeNames));
9519  F->setMetadata("kernel_arg_type_qual", llvm::MDNode::get(C, ArgTypeQuals));
9520  if (CGF.CGM.getCodeGenOpts().EmitOpenCLArgMetadata)
9521  F->setMetadata("kernel_arg_name", llvm::MDNode::get(C, ArgNames));
9522 
9523  return F;
9524 }
const llvm::DataLayout & getDataLayout() const
CGCXXABI & getCXXABI() const
Definition: CodeGenTypes.h:176
Ignore - Ignore the argument (treat as void).
bool isFloatingPoint() const
Definition: Type.h:2443
CharUnits alignTo(const CharUnits &Align) const
alignTo - Returns the next integer (mod 2**64) that is greater than or equal to this quantity and is ...
Definition: CharUnits.h:184
Represents a function declaration or definition.
Definition: Decl.h:1738
void setEffectiveCallingConvention(unsigned Value)
static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD, uint64_t &Size)
if(T->getSizeExpr()) TRY_TO(TraverseStmt(T -> getSizeExpr()))
PointerType - C99 6.7.5.1 - Pointer Declarators.
Definition: Type.h:2537
QualType getPointeeType() const
Definition: Type.h:2550
A (possibly-)qualified type.
Definition: Type.h:638
bool isBlockPointerType() const
Definition: Type.h:6304
base_class_range bases()
Definition: DeclCXX.h:823
bool isMemberPointerType() const
Definition: Type.h:6327
llvm::Type * ConvertTypeForMem(QualType T)
const CodeGenOptions & getCodeGenOpts() const
bool isUnsignedIntegerOrEnumerationType() const
Determines whether this is an integer type that is unsigned or an enumeration types whose underlying ...
Definition: Type.cpp:1900
bool isHomogeneousAggregate(QualType Ty, const Type *&Base, uint64_t &Members) const
isHomogeneousAggregate - Return true if a type is an ELFv2 homogeneous aggregate. ...
static void setCUDAKernelCallingConvention(CanQualType &FTy, CodeGenModule &CGM, const FunctionDecl *FD)
Set calling convention for CUDA/HIP kernel.
Definition: CGCall.cpp:265
Address CreateMemTemp(QualType T, const Twine &Name="tmp", Address *Alloca=nullptr)
CreateMemTemp - Create a temporary memory object of the given type, with appropriate alignmen and cas...
Definition: CGExpr.cpp:139
static ABIArgInfo classifyType(CodeGenModule &CGM, CanQualType type, bool forReturn)
const ASTRecordLayout & getASTRecordLayout(const RecordDecl *D) const
Get or compute information about the layout of the specified record (struct/union/class) D...
Kind getKind() const
Definition: Type.h:2418
FunctionType - C99 6.7.5.3 - Function Declarators.
Definition: Type.h:3355
llvm::ConstantInt * getSize(CharUnits N)
Definition: CGBuilder.h:61
const llvm::Triple & getTriple() const
Returns the target triple of the primary target.
Definition: TargetInfo.h:953
CharUnits getBaseClassOffset(const CXXRecordDecl *Base) const
getBaseClassOffset - Get the offset, in chars, for the given base class.
Definition: RecordLayout.h:233
bool isRealFloatingType() const
Floating point categories.
Definition: Type.cpp:1937
Extend - Valid only for integer argument types.
bool isRecordType() const
Definition: Type.h:6369
Decl - This represents one declaration (or definition), e.g.
Definition: DeclBase.h:87
static bool appendEnumType(SmallStringEnc &Enc, const EnumType *ET, TypeStringCache &TSC, const IdentifierInfo *ID)
Appends enum types to Enc and adds the encoding to the cache.
const RecordType * getAsStructureType() const
Definition: Type.cpp:521
Direct - Pass the argument directly using the normal converted LLVM type, or by coercing to another s...
const llvm::DataLayout & getDataLayout() const
Definition: CodeGenTypes.h:170
StringRef P
static const Type * isSingleElementStruct(QualType T, ASTContext &Context)
isSingleElementStruct - Determine if a structure is a "single element struct", i.e.
Definition: TargetInfo.cpp:536
The base class of the type hierarchy.
Definition: Type.h:1407
const ABIInfo & getABIInfo() const
getABIInfo() - Returns ABI info helper for the target.
Definition: TargetInfo.h:55
Represents an array type, per C99 6.7.5.2 - Array Declarators.
Definition: Type.h:2812
bool isRestrictQualified() const
Determine whether this type is restrict-qualified.
Definition: Type.h:6136
bool isZero() const
isZero - Test whether the quantity equals zero.
Definition: CharUnits.h:116
const TargetInfo & getTargetInfo() const
Definition: ASTContext.h:690
static bool appendType(SmallStringEnc &Enc, QualType QType, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Handles the type&#39;s qualifier before dispatching a call to handle specific type encodings.
llvm::IntegerType * Int8Ty
i8, i16, i32, and i64
void setCanBeFlattened(bool Flatten)
QualType getElementType() const
Definition: Type.h:2847
const RecordType * getAsUnionType() const
NOTE: getAs*ArrayType are methods on ASTContext.
Definition: Type.cpp:540
unsigned getTypeAlign(QualType T) const
Return the ABI-specified alignment of a (complete) type T, in bits.
Definition: ASTContext.h:2091
ASTContext & getContext() const
Definition: TargetInfo.cpp:190
Represents a variable declaration or definition.
Definition: Decl.h:813
LangAS getLangASFromTargetAS(unsigned TargetAS)
Definition: AddressSpaces.h:67
bool isEnumeralType() const
Definition: Type.h:6373
const T * getAs() const
Member-template getAs<specific type>&#39;.
Definition: Type.h:6748
bool hasPointerRepresentation() const
Whether this type is represented natively as a pointer.
Definition: Type.h:6679
LangAS
Defines the address space values used by the address space qualifier of QualType. ...
Definition: AddressSpaces.h:26
llvm::LLVMContext & getVMContext() const
Definition: TargetInfo.cpp:194
void setCoerceToType(llvm::Type *T)
bool field_empty() const
Definition: Decl.h:3792
Address CreateConstInBoundsByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Given a pointer to i8, adjust it by a given constant offset.
Definition: CGBuilder.h:234
llvm::Value * getPointer() const
Definition: Address.h:38
llvm::Type * ConvertTypeForMem(QualType T)
ConvertTypeForMem - Convert type T into a llvm::Type.
static ABIArgInfo getIgnore()
static bool isAggregateTypeForABI(QualType T)
Definition: TargetInfo.cpp:75
bool hasFloatingRepresentation() const
Determine whether this type has a floating-point representation of some sort, e.g., it is a floating-point type or a vector thereof.
Definition: Type.cpp:1930
virtual unsigned getOpenCLKernelCallingConv() const
Get LLVM calling convention for OpenCL kernel.
Definition: TargetInfo.cpp:420
Represents a struct/union/class.
Definition: Decl.h:3593
uint64_t getPointerWidth(unsigned AddrSpace) const
Return the width of pointers on this target, for the specified address space.
Definition: TargetInfo.h:349
static ABIArgInfo coerceToIntArray(QualType Ty, ASTContext &Context, llvm::LLVMContext &LLVMContext)
Definition: TargetInfo.cpp:51
CodeGen::CodeGenTypes & CGT
Definition: ABIInfo.h:53
One of these records is kept for each identifier that is lexed.
Address getAddress() const
Definition: CGValue.h:327
Indirect - Pass the argument indirectly via a hidden pointer with the specified alignment (0 indicate...
CodeGenFunction - This class organizes the per-function state that is used while generating LLVM code...
llvm::Type * ConvertType(QualType T)
ConvertType - Convert type T into a llvm::Type.
Holds long-lived AST nodes (such as types and decls) that can be referred to throughout the semantic ...
Definition: ASTContext.h:155
LineState State
ABIArgInfo classifyArgumentType(CodeGenModule &CGM, CanQualType type)
Classify the rules for how to pass a particular type.
RecordDecl * getDefinition() const
Returns the RecordDecl that actually defines this struct/union/class.
Definition: Decl.h:3774
static llvm::Type * GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi, const llvm::DataLayout &TD)
GetX86_64ByValArgumentPair - Given a high and low type that can ideally be used as elements of a two ...
static CharUnits getTypeAllocSize(CodeGenModule &CGM, llvm::Type *type)
field_range fields() const
Definition: Decl.h:3784
static Address EmitX86_64VAArgFromMemory(CodeGenFunction &CGF, Address VAListAddr, QualType Ty)
Represents a member of a struct/union/class.
Definition: Decl.h:2579
bool isReferenceType() const
Definition: Type.h:6308
CharUnits getTypeUnadjustedAlignInChars(QualType T) const
getTypeUnadjustedAlignInChars - Return the ABI-specified alignment of a type, in characters, before alignment adjustments.
bool isSpecificBuiltinType(unsigned K) const
Test for a particular builtin type.
Definition: Type.h:6511
static CharUnits Zero()
Zero - Construct a CharUnits quantity of zero.
Definition: CharUnits.h:53
static bool occupiesMoreThan(CodeGenTypes &cgt, ArrayRef< llvm::Type *> scalarTypes, unsigned maxAllRegisters)
Does the given lowering require more than the given number of registers when expanded?
Definition: TargetInfo.cpp:113
ABIInfo(CodeGen::CodeGenTypes &cgt)
Definition: ABIInfo.h:57
bool isIntegralOrEnumerationType() const
Determine whether this type is an integral or enumeration type.
Definition: Type.h:6644
static ABIArgInfo getIndirectInReg(CharUnits Alignment, bool ByVal=true, bool Realign=false)
virtual bool hasLegalHalfType() const
Determine whether _Float16 is supported on this target.
Definition: TargetInfo.h:516
virtual StringRef getABI() const
Get the ABI currently in use.
Definition: TargetInfo.h:1019
static ABIArgInfo getDirect(llvm::Type *T=nullptr, unsigned Offset=0, llvm::Type *Padding=nullptr, bool CanBeFlattened=true)
static bool hasScalarEvaluationKind(QualType T)
bool isBitField() const
Determines whether this field is a bitfield.
Definition: Decl.h:2657
static ABIArgInfo getExpandWithPadding(bool PaddingInReg, llvm::Type *Padding)
static bool appendRecordType(SmallStringEnc &Enc, const RecordType *RT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC, const IdentifierInfo *ID)
Appends structure and union types to Enc and adds encoding to cache.
Address CreateElementBitCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Cast the element type of the given address to a different type, preserving information like the align...
Definition: CGBuilder.h:157
CharUnits - This is an opaque type for sizes expressed in character units.
Definition: CharUnits.h:38
const ArrayType * getAsArrayTypeUnsafe() const
A variant of getAs<> for array types which silently discards qualifiers from the outermost type...
Definition: Type.h:6797
CharUnits getAlignment() const
Return the alignment of this pointer.
Definition: Address.h:67
static void rewriteInputConstraintReferences(unsigned FirstIn, unsigned NumNewOuts, std::string &AsmString)
Rewrite input constraint references after adding some output constraints.
static bool isRecordWithSSEVectorType(ASTContext &Context, QualType Ty)
bool isVolatileQualified() const
Determine whether this type is volatile-qualified.
Definition: Type.h:6142
const_arg_iterator arg_begin() const
static ABIArgInfo getExtendInReg(QualType Ty, llvm::Type *T=nullptr)
llvm::CallInst * CreateMemCpy(Address Dest, Address Src, llvm::Value *Size, bool IsVolatile=false)
Definition: CGBuilder.h:274
ABIArgInfo - Helper class to encapsulate information about how a specific C type should be passed to ...
CanQualType LongDoubleTy
Definition: ASTContext.h:1028
const Type * getTypePtr() const
Retrieves a pointer to the underlying (unqualified) type.
Definition: Type.h:6072
unsigned Align
Definition: ASTContext.h:145
field_iterator field_begin() const
Definition: Decl.cpp:4145
llvm::BasicBlock * createBasicBlock(const Twine &name="", llvm::Function *parent=nullptr, llvm::BasicBlock *before=nullptr)
createBasicBlock - Create an LLVM basic block.
static bool BitsContainNoUserData(QualType Ty, unsigned StartBit, unsigned EndBit, ASTContext &Context)
BitsContainNoUserData - Return true if the specified [start,end) bit range is known to either be off ...
static ABIArgInfo getExpand()
bool isFloat128Type() const
Definition: Type.h:6563
bool isScalarType() const
Definition: Type.h:6629
#define UINT_MAX
Definition: limits.h:72
llvm::AllocaInst * CreateTempAlloca(llvm::Type *Ty, const Twine &Name="tmp", llvm::Value *ArraySize=nullptr)
CreateTempAlloca - This creates an alloca and inserts it into the entry block if ArraySize is nullptr...
Definition: CGExpr.cpp:106
unsigned getTypeUnadjustedAlign(QualType T) const
Return the ABI-specified natural alignment of a (complete) type T, before alignment adjustments...
Definition: ASTContext.h:2099
constexpr XRayInstrMask All
Definition: XRayInstr.h:42
const T * getTypePtr() const
Retrieve the underlying type pointer, which refers to a canonical type.
Definition: CanonicalType.h:84
static QualType useFirstFieldIfTransparentUnion(QualType Ty)
Pass transparent unions as if they were the type of the first element.
Definition: TargetInfo.cpp:175
virtual llvm::Value * performAddrSpaceCast(CodeGen::CodeGenFunction &CGF, llvm::Value *V, LangAS SrcAddr, LangAS DestAddr, llvm::Type *DestTy, bool IsNonNull=false) const
Perform address space cast of an expression of pointer type.
Definition: TargetInfo.cpp:447
bool isTypeConstant(QualType QTy, bool ExcludeCtorDtor)
isTypeConstant - Determine whether an object of this type can be emitted as a constant.
ExtInfo withCallingConv(CallingConv cc) const
Definition: Type.h:3571
Represents a K&R-style &#39;int foo()&#39; function, which has no information available about its arguments...
Definition: Type.h:3650
static bool ContainsFloatAtOffset(llvm::Type *IRType, unsigned IROffset, const llvm::DataLayout &TD)
ContainsFloatAtOffset - Return true if the specified LLVM IR type has a float member at the specified...
bool isHalfType() const
Definition: Type.h:6550
static ABIArgInfo getSignExtend(QualType Ty, llvm::Type *T=nullptr)
bool hasAttr() const
Definition: DeclBase.h:531
CanQualType getReturnType() const
return Out str()
bool isPromotableIntegerType() const
More type predicates useful for type checking/promotion.
Definition: Type.cpp:2455
static CharUnits One()
One - Construct a CharUnits quantity of one.
Definition: CharUnits.h:58
Represents a prototype with parameter type info, e.g.
Definition: Type.h:3687
virtual CodeGen::Address EmitMSVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const
Emit the target dependent code to load a value of.
Definition: TargetInfo.cpp:93
const TargetCodeGenInfo & getTargetCodeGenInfo()
bool isComplexType() const
isComplexType() does not include complex integers (a GCC extension).
Definition: Type.cpp:481
static bool extractFieldType(SmallVectorImpl< FieldEncoding > &FE, const RecordDecl *RD, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Helper function for appendRecordType().
virtual void getDependentLibraryOption(llvm::StringRef Lib, llvm::SmallString< 24 > &Opt) const
Gets the linker options necessary to link a dependent library on this platform.
Definition: TargetInfo.cpp:411
static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, llvm::Value *Array, llvm::Value *Value, unsigned FirstIndex, unsigned LastIndex)
Definition: TargetInfo.cpp:62
static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context)
void setAddress(Address address)
Definition: CGValue.h:328
QuantityType getQuantity() const
getQuantity - Get the raw integer representation of this quantity.
Definition: CharUnits.h:179
unsigned Offset
Definition: Format.cpp:1631
ASTRecordLayout - This class contains layout information for one RecordDecl, which is a struct/union/...
Definition: RecordLayout.h:39
const llvm::fltSemantics & getLongDoubleFormat() const
Definition: TargetInfo.h:579
Exposes information about the current target.
Definition: TargetInfo.h:54
CodeGen::ABIArgInfo getNaturalAlignIndirect(QualType Ty, bool ByRef=true, bool Realign=false, llvm::Type *Padding=nullptr) const
A convenience method to return an indirect ABIArgInfo with an expected alignment equal to the ABI ali...
Definition: TargetInfo.cpp:81
QualType getElementType() const
Definition: Type.h:2490
QualType getVectorType(QualType VectorType, unsigned NumElts, VectorType::VectorKind VecKind) const
Return the unique reference to a vector type of the specified element type and size.
static ABIArgInfo getExtend(QualType Ty, llvm::Type *T=nullptr)
static Address invalid()
Definition: Address.h:35
const IdentifierInfo * getBaseTypeIdentifier() const
Retrieves a pointer to the name of the base type.
Definition: Type.cpp:71
static bool appendBuiltinType(SmallStringEnc &Enc, const BuiltinType *BT)
Appends built-in types to Enc.
field_iterator field_end() const
Definition: Decl.h:3787
virtual bool classifyReturnType(CGFunctionInfo &FI) const =0
If the C++ ABI requires the given type be returned in a particular way, this method sets RetAI and re...
llvm::PointerType * getType() const
Return the type of the pointer value.
Definition: Address.h:44
CharUnits getTypeAlignInChars(QualType T) const
Return the ABI-specified alignment of a (complete) type T, in characters.
bool isAnyComplexType() const
Definition: Type.h:6377
static CharUnits fromQuantity(QuantityType Quantity)
fromQuantity - Construct a CharUnits quantity from a raw integer type.
Definition: CharUnits.h:63
static bool getTypeString(SmallStringEnc &Enc, const Decl *D, CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
The XCore ABI includes a type information section that communicates symbol type information to the li...
unsigned getFieldCount() const
getFieldCount - Get the number of fields in the layout.
Definition: RecordLayout.h:187
EnumDecl * getDefinition() const
Definition: Decl.h:3427
llvm::CallingConv::ID RuntimeCC
Definition: ABIInfo.h:55
static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI, const ABIInfo &Info)
Definition: TargetInfo.cpp:159
llvm::LLVMContext & getLLVMContext()
bool isSignedIntegerType() const
Return true if this is an integer type that is signed, according to C99 6.2.5p4 [char, signed char, short, int, long..], or an enum decl which has a signed representation.
Definition: Type.cpp:1844
CodeGen::ABIArgInfo getNaturalAlignIndirectInReg(QualType Ty, bool Realign=false) const
Definition: TargetInfo.cpp:88
const CodeGenOptions & getCodeGenOpts() const
CharUnits alignmentOfArrayElement(CharUnits elementSize) const
Given that this is the alignment of the first element of an array, return the minimum alignment of an...
Definition: CharUnits.h:197
static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, Address VAListAddr, llvm::Type *DirectTy, CharUnits DirectSize, CharUnits DirectAlign, CharUnits SlotSize, bool AllowHigherAlign)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
Definition: TargetInfo.cpp:288
Represents a GCC generic vector type.
Definition: Type.h:3168
ArraySizeModifier getSizeModifier() const
Definition: Type.h:2849
virtual unsigned getSizeOfUnwindException() const
Determines the size of struct _Unwind_Exception on this platform, in 8-bit units. ...
Definition: TargetInfo.cpp:391
Implements C++ ABI-specific semantic analysis functions.
Definition: CXXABI.h:30
const TargetInfo & getTarget() const
bool isUnionType() const
Definition: Type.cpp:475
const LangOptions & getLangOpts() const
ASTContext & getContext() const
bool isNull() const
Return true if this QualType doesn&#39;t point to a type yet.
Definition: Type.h:703
Attempt to be ABI-compatible with code generated by Clang 3.8.x (SVN r257626).
virtual llvm::Constant * getNullPointer(const CodeGen::CodeGenModule &CGM, llvm::PointerType *T, QualType QT) const
Get target specific null pointer.
Definition: TargetInfo.cpp:434
CallingConv
CallingConv - Specifies the calling convention that a function uses.
Definition: Specifiers.h:236
bool isConstQualified() const
Determine whether this type is const-qualified.
Definition: Type.h:6131
The l-value was considered opaque, so the alignment was determined from a type.
RecordDecl * getDecl() const
Definition: Type.h:4380
Pass it as a pointer to temporary memory.
Definition: CGCXXABI.h:137
uint64_t getFieldOffset(unsigned FieldNo) const
getFieldOffset - Get the offset of the given field index, in bits.
Definition: RecordLayout.h:191
bool isStructureOrClassType() const
Definition: Type.cpp:461
static void appendQualifier(SmallStringEnc &Enc, QualType QT)
Appends type&#39;s qualifier to Enc.
static Address emitMergePHI(CodeGenFunction &CGF, Address Addr1, llvm::BasicBlock *Block1, Address Addr2, llvm::BasicBlock *Block2, const llvm::Twine &Name="")
Definition: TargetInfo.cpp:375
static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, bool AllowArrays)
isEmptyField - Return true iff a the field is "empty", that is it is an unnamed bit-field or an (arra...
Definition: TargetInfo.cpp:475
Address CreateBitCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Definition: CGBuilder.h:142
Kind
QualType getCanonicalType() const
Definition: Type.h:6111
bool isBuiltinType() const
Helper methods to distinguish type categories.
Definition: Type.h:6365
QualType getReturnType() const
Definition: Type.h:3613
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of enums...
Definition: Type.h:4396
LangAS getAddressSpace() const
Return the address space of this type.
Definition: Type.h:6188
const TargetInfo & getTarget() const
Definition: TargetInfo.cpp:202
bool isUnnamedBitfield() const
Determines whether this is an unnamed bitfield.
Definition: Decl.h:2660
static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays)
isEmptyRecord - Return true iff a structure contains only empty fields.
Definition: TargetInfo.cpp:508
static bool appendFunctionType(SmallStringEnc &Enc, const FunctionType *FT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Appends a function encoding to Enc, calling appendType for the return type and the arguments...
SyncScope
Defines synch scope values used internally by clang.
Definition: SyncScope.h:43
const llvm::DataLayout & getDataLayout() const
Definition: TargetInfo.cpp:198
void setArgStruct(llvm::StructType *Ty, CharUnits Align)
virtual void computeInfo(CodeGen::CGFunctionInfo &FI) const =0
const ConstantArrayType * getAsConstantArrayType(QualType T) const
Definition: ASTContext.h:2413
const_arg_iterator arg_end() const
CanQualType FloatTy
Definition: ASTContext.h:1028
CoerceAndExpand - Only valid for aggregate argument types.
bool isSignedIntegerOrEnumerationType() const
Determines whether this is an integer type that is signed or an enumeration types whose underlying ty...
Definition: Type.cpp:1860
bool isMemberFunctionPointerType() const
Definition: Type.h:6331
An aligned address.
Definition: Address.h:25
llvm::LLVMContext & getLLVMContext()
Definition: CodeGenTypes.h:177
bool canPassInRegisters() const
Determine whether this class can be passed in registers.
Definition: Decl.h:3719
constexpr XRayInstrMask None
Definition: XRayInstr.h:38
bool operator<(DeclarationName LHS, DeclarationName RHS)
Ordering on two declaration names.
bool isTargetAddressSpace(LangAS AS)
Definition: AddressSpaces.h:58
EnumDecl * getDecl() const
Definition: Type.h:4403
bool isVectorType() const
Definition: Type.h:6381
TargetCodeGenInfo - This class organizes various target-specific codegeneration issues, like target-specific attributes, builtins and so on.
Definition: TargetInfo.h:46
InAlloca - Pass the argument directly using the LLVM inalloca attribute.
X86AVXABILevel
The AVX ABI level for X86 targets.
QualType getType() const
Definition: CGValue.h:264
llvm::CallingConv::ID getRuntimeCC() const
Return the calling convention to use for system runtime functions.
Definition: ABIInfo.h:73
bool hasFlexibleArrayMember() const
Definition: Decl.h:3647
static llvm::Value * emitRoundPointerUpToAlignment(CodeGenFunction &CGF, llvm::Value *Ptr, CharUnits Align)
Definition: TargetInfo.cpp:258
CanProxy< U > getAs() const
Retrieve a canonical type pointer with a different static type, upcasting or downcasting as needed...
std::pair< CharUnits, CharUnits > getTypeInfoInChars(const Type *T) const
llvm::Type * getPaddingType() const
StringRef getName() const
Return the actual identifier string.
const TargetInfo & getTarget() const
Definition: CodeGenTypes.h:175
virtual CodeGen::Address EmitVAArg(CodeGen::CodeGenFunction &CGF, CodeGen::Address VAListAddr, QualType Ty) const =0
EmitVAArg - Emit the target dependent code to load a value of.
CGFunctionInfo - Class to encapsulate the information about a function definition.
This class organizes the cross-function state that is used while generating LLVM code.
Dataflow Directional Tag Classes.
bool isFloat16Type() const
Definition: Type.h:6557
virtual LangAS getGlobalVarAddressSpace(CodeGenModule &CGM, const VarDecl *D) const
Get target favored AST address space of a global variable for languages other than OpenCL and CUDA...
Definition: TargetInfo.cpp:439
ExtInfo getExtInfo() const
Definition: Type.h:3624
A refining implementation of ABIInfo for targets that support swiftcall.
Definition: ABIInfo.h:124
static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD, uint64_t &Size)
virtual llvm::Function * createEnqueuedBlockKernel(CodeGenFunction &CGF, llvm::Function *BlockInvokeFunc, llvm::Value *BlockLiteral) const
Create an OpenCL kernel for an enqueued block.
static ABIArgInfo getDirectInReg(llvm::Type *T=nullptr)
Address CreateStructGEP(Address Addr, unsigned Index, CharUnits Offset, const llvm::Twine &Name="")
Definition: CGBuilder.h:172
virtual bool isHomogeneousAggregateSmallEnough(const Type *Base, uint64_t Members) const
Definition: TargetInfo.cpp:216
llvm::LoadInst * CreateAlignedLoad(llvm::Value *Addr, CharUnits Align, const llvm::Twine &Name="")
Definition: CGBuilder.h:91
static bool appendArrayType(SmallStringEnc &Enc, QualType QT, const ArrayType *AT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC, StringRef NoSizeEnc)
Appends array encoding to Enc before calling appendType for the element.
llvm::LoadInst * CreateLoad(Address Addr, const llvm::Twine &Name="")
Definition: CGBuilder.h:70
Represents an enum.
Definition: Decl.h:3326
virtual bool isNoProtoCallVariadic(const CodeGen::CallArgList &args, const FunctionNoProtoType *fnType) const
Determine whether a call to an unprototyped functions under the given calling convention should use t...
Definition: TargetInfo.cpp:401
llvm::StoreInst * CreateStore(llvm::Value *Val, Address Addr, bool IsVolatile=false)
Definition: CGBuilder.h:108
bool isAggregateType() const
Determines whether the type is a C++ aggregate type or C aggregate or union type. ...
Definition: Type.cpp:2007
llvm::Module & getModule() const
virtual bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy, unsigned elts) const
Definition: TargetInfo.cpp:132
LValue MakeAddrLValue(Address Addr, QualType T, AlignmentSource Source=AlignmentSource::Type)
specific_decl_iterator - Iterates over a subrange of declarations stored in a DeclContext, providing only those that are of type SpecificDecl (or a class derived from it).
Definition: DeclBase.h:2017
unsigned getIntWidth(QualType T) const
virtual void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const
setTargetAttributes - Provides a convenient hook to handle extra target-specific attributes for the g...
Definition: TargetInfo.h:59
virtual llvm::Optional< LangAS > getConstantAddressSpace() const
Return an AST address space which can be used opportunistically for constant global memory...
Definition: TargetInfo.h:1205
A helper class that allows the use of isa/cast/dyncast to detect TagType objects of structs/unions/cl...
Definition: Type.h:4370
Complex values, per C99 6.2.5p11.
Definition: Type.h:2477
Pass it using the normal C aggregate rules for the ABI, potentially introducing extra copies and pass...
Definition: CGCXXABI.h:129
Address CreateConstArrayGEP(Address Addr, uint64_t Index, CharUnits EltSize, const llvm::Twine &Name="")
Given addr = [n x T]* ...
Definition: CGBuilder.h:195
bool isIntegerType() const
isIntegerType() does not include complex integers (a GCC extension).
Definition: Type.h:6578
void EmitStoreOfComplex(ComplexPairTy V, LValue dest, bool isInit)
EmitStoreOfComplex - Store a complex number into the specified l-value.
Implements C++ ABI-specific code generation functions.
Definition: CGCXXABI.h:44
T * getAttr() const
Definition: DeclBase.h:527
llvm::Type * getElementType() const
Return the type of the values stored in this address.
Definition: Address.h:52
This class organizes the cross-module state that is used while lowering AST types to LLVM types...
Definition: CodeGenTypes.h:119
CodeGen::CGCXXABI & getCXXABI() const
Definition: TargetInfo.cpp:186
CodeGenOptions - Track various options which control how the code is optimized and passed to the back...
Expand - Only valid for aggregate argument types.
Internal linkage, which indicates that the entity can be referred to from within the translation unit...
Definition: Linkage.h:32
virtual bool hasFloat128Type() const
Determine whether the __float128 type is supported on this target.
Definition: TargetInfo.h:519
void EmitBlock(llvm::BasicBlock *BB, bool IsFinished=false)
EmitBlock - Emit the given block.
Definition: CGStmt.cpp:443
static bool isArgInAlloca(const ABIArgInfo &Info)
static ABIArgInfo getInAlloca(unsigned FieldIndex)
Represents a base class of a C++ class.
Definition: DeclCXX.h:192
uint64_t getTypeSize(QualType T) const
Return the size of the specified (complete) type T, in bits.
Definition: ASTContext.h:2070
ASTContext & getContext() const
Definition: CodeGenTypes.h:173
Pass it on the stack using its defined layout.
Definition: CGCXXABI.h:134
static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, CGCXXABI &CXXABI)
Definition: TargetInfo.cpp:140
CanQualType getCanonicalType(QualType T) const
Return the canonical (structural) type corresponding to the specified potentially non-canonical type ...
Definition: ASTContext.h:2253
CharUnits toCharUnitsFromBits(int64_t BitSize) const
Convert a size in bits to a size in characters.
bool isMultipleOf(CharUnits N) const
Test whether this is a multiple of the other value.
Definition: CharUnits.h:137
int64_t toBits(CharUnits CharSize) const
Convert a size in characters to a size in bits.
virtual llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext &C) const
Get the syncscope used in LLVM IR.
Definition: TargetInfo.cpp:467
CallingConv getCallConv() const
Definition: Type.h:3623
unsigned getCallingConvention() const
getCallingConvention - Return the user specified calling convention, which has been translated into a...
Address CreateConstByteGEP(Address Addr, CharUnits Offset, const llvm::Twine &Name="")
Definition: CGBuilder.h:240
Represents a C++ struct/union/class.
Definition: DeclCXX.h:300
void EmitBranch(llvm::BasicBlock *Block)
EmitBranch - Emit a branch to the specified basic block from the current insert block, taking care to avoid creation of branches from dummy blocks.
Definition: CGStmt.cpp:463
bool isVoidType() const
Definition: Type.h:6544
TypeInfo getTypeInfo(const Type *T) const
Get the size and alignment of the specified complete type in bits.
llvm::Type * ConvertType(QualType T)
virtual RecordArgABI getRecordArgABI(const CXXRecordDecl *RD) const =0
Returns how an argument of the given record type should be passed.
QualType getPointerType(QualType T) const
Return the uniqued reference to the type for a pointer to the specified type.
This class is used for builtin types like &#39;int&#39;.
Definition: Type.h:2391
static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType ValueTy, bool IsIndirect, std::pair< CharUnits, CharUnits > ValueInfo, CharUnits SlotSizeAndAlign, bool AllowHigherAlign)
Emit va_arg for a platform using the common void* representation, where arguments are simply emitted ...
Definition: TargetInfo.cpp:342
ABIInfo - Target specific hooks for defining how a type should be passed or returned from functions...
Definition: ABIInfo.h:51
uint64_t Width
Definition: ASTContext.h:144
__DEVICE__ int max(int __a, int __b)
static bool appendPointerType(SmallStringEnc &Enc, const PointerType *PT, const CodeGen::CodeGenModule &CGM, TypeStringCache &TSC)
Appends a pointer encoding to Enc before calling appendType for the pointee.
uint64_t getTargetNullPointerValue(QualType QT) const
Get target-dependent integer value for null pointer which is used for constant folding.
virtual bool isHomogeneousAggregateBaseType(QualType Ty) const
Definition: TargetInfo.cpp:212
bool isUnion() const
Definition: Decl.h:3252
bool isPointerType() const
Definition: Type.h:6296
unsigned getNumRequiredArgs() const
__DEVICE__ int min(int __a, int __b)
unsigned getDirectOffset() const
CharUnits getTypeSizeInChars(QualType T) const
Return the size of the specified (complete) type T, in characters.
llvm::StoreInst * CreateAlignedStore(llvm::Value *Val, llvm::Value *Addr, CharUnits Align, bool IsVolatile=false)
Definition: CGBuilder.h:115
void computeSPIRKernelABIInfo(CodeGenModule &CGM, CGFunctionInfo &FI)
QualType getType() const
Definition: Decl.h:648
bool isFloatingType() const
Definition: Type.cpp:1921
LValue - This represents an lvalue references.
Definition: CGValue.h:167
llvm::Type * getCoerceToType() const
void setInAllocaSRet(bool SRet)
unsigned getTargetAddressSpace(QualType T) const
Definition: ASTContext.h:2499
CanQualType DoubleTy
Definition: ASTContext.h:1028
RecordArgABI
Specify how one should pass an argument of a record type.
Definition: CGCXXABI.h:126
Address CreatePointerBitCastOrAddrSpaceCast(Address Addr, llvm::Type *Ty, const llvm::Twine &Name="")
Definition: CGBuilder.h:164
static bool isIntegerLikeType(QualType Ty, ASTContext &Context, llvm::LLVMContext &VMContext)
static bool isSSEVectorType(ASTContext &Context, QualType Ty)
CallArgList - Type for representing both the value and type of arguments in a call.
Definition: CGCall.h:260
const LangOptions & getLangOpts() const
Definition: ASTContext.h:707
static bool PPC64_initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, llvm::Value *Address)
Represents the canonical version of C arrays with a specified constant size.
Definition: Type.h:2872
static ABIArgInfo getIndirect(CharUnits Alignment, bool ByVal=true, bool Realign=false, llvm::Type *Padding=nullptr)
Attr - This represents one attribute.
Definition: Attr.h:44
QualType getIntTypeForBitwidth(unsigned DestWidth, unsigned Signed) const
getIntTypeForBitwidth - sets integer QualTy according to specified details: bitwidth, signed/unsigned.
static OMPLinearClause * Create(const ASTContext &C, SourceLocation StartLoc, SourceLocation LParenLoc, OpenMPLinearClauseKind Modifier, SourceLocation ModifierLoc, SourceLocation ColonLoc, SourceLocation EndLoc, ArrayRef< Expr *> VL, ArrayRef< Expr *> PL, ArrayRef< Expr *> IL, Expr *Step, Expr *CalcStep, Stmt *PreInit, Expr *PostUpdate)
Creates clause with a list of variables VL and a linear step Step.
const CodeGenOptions & getCodeGenOpts() const
Definition: TargetInfo.cpp:206
const llvm::Triple & getTriple() const